Experimental use of the Xilinx FPGA development tools ISE6.x, create a new project, and comprehensive, the layout of wiring, download configuration. The establishment of the project here is to use Create-SOPCMB on the eight light-emitting diode displays a binary counter, said the light-emitting diode light-bit to 0.

Exp1-Led
........\automake.log
........\BinaryCounter.vhdl
........\bitgen.ut
........\coregen.log
........\coregen.prj
........\Lab1.dhp
........\Lab1.ise
........\Lab1.ise_ISE_Backup
........\Lab1_ise6_bak.zip
........\myucf.ucf
........\myucf.ucf.untf
........\top.bgn
........\top.bit
........\top.bld
........\top.cmd_log
........\top.drc
........\top.lso
........\top.mrp
........\top.nc1
........\top.ncd
........\top.ngc
........\top.ngd
........\top.ngm
........\top.ngr
........\top.pad
........\top.pad_txt
........\top.par
........\top.pcf
........\top.placed_ncd_tracker
........\top.prj
........\top.routed_ncd_tracker
........\top.stx
........\top.syr
........\top.twr
........\top.twx
........\top.ut
........\top.xpi
........\top_last_par.ncd
........\top_map.ncd
........\top_map.ngm
........\top_pad.csv
........\top_pad.txt
........\top_summary.html
........\untitled.cdf
........\xst
........\...\work
........\...\....\hdllib.ref
........\...\....\hdpdeps.ref
........\...\....\sub00
........\...\....\.....\vhpl00.vho
........\...\....\.....\vhpl01.vho
........\_impact.cmd
........\_impact.log
........\_ngo
........\....\netlist.lst
........\_xmsgs
........\__projnav
........\.........\bitgen.rsp
........\.........\coregen.rsp
........\.........\ednTOngd_tcl.rsp
........\.........\Lab1.gfl
........\.........\Lab1_flowplus.gfl
........\.........\map.log
........\.........\nc1TOncd_tcl.rsp
........\.........\par.log
........\.........\posttrc.log
........\.........\runXst_tcl.rsp
........\.........\sumrpt_tcl.rsp
........\.........\top.xst
........\.........\top_ncdTOut_tcl.rsp
........\.........\tozp_tcl.rsp
........\__projnav.log

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