File Format: VHDL language. According to the specific needs of their own prepared, and timing simulation entirely correct. Procedures can be directly diverted to extract, and then open the Quartus II compiler and simulation. Very convenient, easy to use!

div-8.5
.......\clk_div4.asm.rpt
.......\clk_div4.bsf
.......\clk_div4.done
.......\clk_div4.fit.rpt
.......\clk_div4.fit.smsg
.......\clk_div4.fit.summary
.......\clk_div4.flow.rpt
.......\clk_div4.map.rpt
.......\clk_div4.map.summary
.......\clk_div4.pin
.......\clk_div4.pof
.......\clk_div4.qpf
.......\clk_div4.qsf
.......\clk_div4.qws
.......\clk_div4.sim.rpt
.......\clk_div4.sof
.......\clk_div4.tan.rpt
.......\clk_div4.tan.summary
.......\clk_div4.vhd
.......\clk_div4.vhd.bak
.......\clk_div4.vwf
.......\db
.......\..\clk_div4.asm.qmsg
.......\..\clk_div4.asm_labs.ddb
.......\..\clk_div4.cbx.xml
.......\..\clk_div4.cmp.bpm
.......\..\clk_div4.cmp.cdb
.......\..\clk_div4.cmp.ecobp
.......\..\clk_div4.cmp.hdb
.......\..\clk_div4.cmp.logdb
.......\..\clk_div4.cmp.rdb
.......\..\clk_div4.cmp.tdb
.......\..\clk_div4.cmp0.ddb
.......\..\clk_div4.cmp_bb.cdb
.......\..\clk_div4.cmp_bb.hdb
.......\..\clk_div4.cmp_bb.logdb
.......\..\clk_div4.cmp_bb.rcf
.......\..\clk_div4.dbp
.......\..\clk_div4.db_info
.......\..\clk_div4.eco.cdb
.......\..\clk_div4.eds_overflow
.......\..\clk_div4.fit.qmsg
.......\..\clk_div4.hier_info
.......\..\clk_div4.hif
.......\..\clk_div4.map.bpm
.......\..\clk_div4.map.cdb
.......\..\clk_div4.map.ecobp
.......\..\clk_div4.map.hdb
.......\..\clk_div4.map.logdb
.......\..\clk_div4.map.qmsg
.......\..\clk_div4.map_bb.cdb
.......\..\clk_div4.map_bb.hdb
.......\..\clk_div4.map_bb.logdb
.......\..\clk_div4.pre_map.cdb
.......\..\clk_div4.pre_map.hdb
.......\..\clk_div4.psp
.......\..\clk_div4.pss
.......\..\clk_div4.rtlv.hdb
.......\..\clk_div4.rtlv_sg.cdb
.......\..\clk_div4.rtlv_sg_swap.cdb
.......\..\clk_div4.sgdiff.cdb
.......\..\clk_div4.sgdiff.hdb
.......\..\clk_div4.signalprobe.cdb
.......\..\clk_div4.sim.cvwf
.......\..\clk_div4.sim.hdb
.......\..\clk_div4.sim.qmsg
.......\..\clk_div4.sim.rdb
.......\..\clk_div4.sld_design_entry.sci
.......\..\clk_div4.sld_design_entry_dsc.sci
.......\..\clk_div4.syn_hier_info
.......\..\clk_div4.tan.qmsg
.......\..\prev_cmp_clk_div4.asm.qmsg
.......\..\prev_cmp_clk_div4.fit.qmsg
.......\..\prev_cmp_clk_div4.map.qmsg
.......\..\prev_cmp_clk_div4.sim.qmsg
.......\..\prev_cmp_clk_div4.tan.qmsg
.......\..\wed.wsf
.......\prev_cmp_clk_div4.qmsg

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