With the FPGA module pll digital clock with a simulation file.

Seg7_dsp
........\cmp_state.ini
........\code.vhd
........\code.vhd.bak
........\COUNTER24.VHD
........\COUNTER60.VHD
........\db
........\..\prev_cmp_Seg7_dsp.asm.qmsg
........\..\prev_cmp_Seg7_dsp.fit.qmsg
........\..\prev_cmp_Seg7_dsp.map.qmsg
........\..\prev_cmp_Seg7_dsp.qmsg
........\..\prev_cmp_Seg7_dsp.sim.qmsg
........\..\prev_cmp_Seg7_dsp.tan.qmsg
........\..\Seg7_dsp.asm.qmsg
........\..\Seg7_dsp.asm_labs.ddb
........\..\Seg7_dsp.cbx.xml
........\..\Seg7_dsp.cmp.cdb
........\..\Seg7_dsp.cmp.hdb
........\..\Seg7_dsp.cmp.logdb
........\..\Seg7_dsp.cmp.rdb
........\..\Seg7_dsp.cmp.tdb
........\..\Seg7_dsp.cmp0.ddb
........\..\Seg7_dsp.dbp
........\..\Seg7_dsp.db_info
........\..\Seg7_dsp.eco.cdb
........\..\Seg7_dsp.eds_overflow
........\..\Seg7_dsp.fit.qmsg
........\..\Seg7_dsp.hier_info
........\..\Seg7_dsp.hif
........\..\Seg7_dsp.map.cdb
........\..\Seg7_dsp.map.hdb
........\..\Seg7_dsp.map.logdb
........\..\Seg7_dsp.map.qmsg
........\..\Seg7_dsp.pre_map.cdb
........\..\Seg7_dsp.pre_map.hdb
........\..\Seg7_dsp.psp
........\..\Seg7_dsp.pss
........\..\Seg7_dsp.rpp.qmsg
........\..\Seg7_dsp.rtlv.hdb
........\..\Seg7_dsp.rtlv_sg.cdb
........\..\Seg7_dsp.rtlv_sg_swap.cdb
........\..\Seg7_dsp.sgate.rvd
........\..\Seg7_dsp.sgate_sm.rvd
........\..\Seg7_dsp.sgdiff.cdb
........\..\Seg7_dsp.sgdiff.hdb
........\..\Seg7_dsp.signalprobe.cdb
........\..\Seg7_dsp.sim.cvwf
........\..\Seg7_dsp.sim.hdb
........\..\Seg7_dsp.sim.qmsg
........\..\Seg7_dsp.sim.rdb
........\..\Seg7_dsp.sld_design_entry.sci
........\..\Seg7_dsp.sld_design_entry_dsc.sci
........\..\Seg7_dsp.syn_hier_info
........\..\Seg7_dsp.tan.qmsg
........\..\Seg7_dsp.tis_db_list.ddb
........\..\Seg7_dsp_cmp.qrpt
........\..\wed.wsf
........\pll_cp.cmp
........\pll_cp.ppf
........\pll_cp.vhd

........\pll_cp_waveforms.html
........\Seg7_dsp.asm.rpt
........\Seg7_dsp.done
........\Seg7_dsp.dpf
........\Seg7_dsp.fit.eqn
........\Seg7_dsp.fit.rpt
........\Seg7_dsp.fit.smsg
........\Seg7_dsp.fit.summary
........\Seg7_dsp.flow.rpt
........\Seg7_dsp.map.eqn
........\Seg7_dsp.map.rpt
........\Seg7_dsp.map.summary
........\Seg7_dsp.pin
........\Seg7_dsp.pof
........\Seg7_dsp.qpf
........\Seg7_dsp.qsf
........\Seg7_dsp.qws
........\Seg7_dsp.sim.rpt
........\Seg7_dsp.sof
........\Seg7_dsp.tan.rpt
........\Seg7_dsp.tan.summary
........\Seg7_dsp.vhd
........\Seg7_dsp.vhd.bak
........\Seg7_dsp.vwf
........\Seg7_dsp_assignment_defaults.qdf
........\seg_code.vhd
........\seg_code.vhd.bak

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