Verilog and VHDL based on the DDS process VHDL-based 8-bit decimal Cymometer

EDA_project
...........\DDS
...........\...\adder32.vhd
...........\...\db
...........\...\..\add_sub_hjh.tdf
...........\...\..\dds.asm.qmsg
...........\...\..\dds.cbx.xml
...........\...\..\dds.cmp.cdb
...........\...\..\dds.cmp.hdb
...........\...\..\dds.cmp.logdb
...........\...\..\dds.cmp.rdb
...........\...\..\dds.cmp.tdb
...........\...\..\dds.cmp0.ddb
...........\...\..\dds.dbp
...........\...\..\dds.db_info
...........\...\..\dds.eco.cdb
...........\...\..\dds.fit.qmsg
...........\...\..\dds.hier_info
...........\...\..\dds.hif
...........\...\..\dds.map.cdb
...........\...\..\dds.map.hdb
...........\...\..\dds.map.logdb
...........\...\..\dds.map.qmsg
...........\...\..\dds.pre_map.cdb
...........\...\..\dds.pre_map.hdb
...........\...\..\dds.psp
...........\...\..\dds.rtlv.hdb
...........\...\..\dds.rtlv_sg.cdb
...........\...\..\dds.rtlv_sg_swap.cdb
...........\...\..\dds.sgdiff.cdb
...........\...\..\dds.sgdiff.hdb
...........\...\..\dds.sld_design_entry.sci
...........\...\..\dds.sld_design_entry_dsc.sci
...........\...\..\dds.syn_hier_info
...........\...\..\dds.tan.qmsg
...........\...\dds.asm.rpt
...........\...\dds.done
...........\...\dds.fit.rpt
...........\...\dds.fit.summary
...........\...\dds.flow.rpt
...........\...\dds.map.rpt
...........\...\dds.map.summary
...........\...\dds.pin
...........\...\dds.pof
...........\...\dds.qpf
...........\...\dds.qsf
...........\...\dds.qws
...........\...\dds.sof
...........\...\dds.tan.rpt
...........\...\dds.tan.summary
...........\...\dds.vhd
...........\...\reg1.vhd
...........\...\reg2.vhd
...........\...\sum32.vhd
...........\DDS_verilog
...........\...........\db
...........\...........\..\wave.asm.qmsg
...........\...........\..\wave.cbx.xml
...........\...........\..\wave.cmp.cdb
...........\...........\..\wave.cmp.hdb
...........\...........\..\wave.cmp.kpt
...........\...........\..\wave.cmp.logdb
...........\...........\..\wave.cmp.rdb
...........\...........\..\wave.cmp.tdb
...........\...........\..\wave.cmp0.ddb
...........\...........\..\wave.dbp
...........\...........\..\wave.db_info
...........\...........\..\wave.eco.cdb
...........\...........\..\wave.fit.qmsg
...........\...........\..\wave.hier_info
...........\...........\..\wave.hif
...........\...........\..\wave.map.cdb
...........\...........\..\wave.map.hdb
...........\...........\..\wave.map.logdb
...........\...........\..\wave.map.qmsg
...........\...........\..\wave.pre_map.cdb
...........\...........\..\wave.pre_map.hdb
...........\...........\..\wave.psp
...........\...........\..\wave.rpp.qmsg
...........\...........\..\wave.rtlv.hdb
...........\...........\..\wave.rtlv_sg.cdb
...........\...........\..\wave.rtlv_sg_swap.cdb
...........\...........\..\wave.sgate.rvd
...........\...........\..\wave.sgate_sm.rvd
...........\...........\..\wave.sgdiff.cdb
...........\...........\..\wave.sgdiff.hdb
...........\...........\..\wave.signalprobe.cdb
...........\...........\..\wave.sld_design_entry.sci
...........\...........\..\wave.sld_design_entry_dsc.sci
...........\...........\..\wave.syn_hier_info
...........\...........\..\wave.tan.qmsg
...........\...........\test_ACC.v
...........\...........\test_ACC_ADD.v
...........\...........\test_ADDP.v
...........\...........\test_wave.v
...........\...........\test_wave_rom.v
...........\...........\wave.asm.rpt
...........\...........\wave.done
...........\...........\wave.dpf
...........\...........\wave.fit.rpt

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