This FPGA project include a simple version of the UART for Actel Igloo nano.

Src
...\applic.vhd
...\top_uart.vhd
...\uart2400.vhd
...\waveperl.log
top_uart
........\component
........\constraint
........\coreconsole
........\designer
........\........\impl1
........\........\.....\APPLIC.ide_des
........\........\.....\designer.log
........\........\.....\simulation
........\........\.....\TOP_UART.adb
........\........\.....\TOP_UART.dtf
........\........\.....\............\verify.log
........\........\.....\TOP_UART.ide_des
........\........\.....\TOP_UART.pdb
........\........\.....\TOP_UART.pdb.depends
........\........\.....\TOP_UART.tcl
........\........\.....\TOP_UART_fp
........\........\.....\...........\$$FlashPro_70434.L$$
........\........\.....\...........\TOP_UART.log
........\........\.....\...........\TOP_UART.pro
........\hdl
........\phy_synthesis
........\simulation
........\..........\modelsim.ini
........\..........\modelsim.ini.sav
........\smartgen
........\........\smartgen.aws
........\stimulus
........\synthesis
........\.........\.recordref
........\.........\backup
........\.........\......\TOP_UART.srr
........\.........\coreip
........\.........\run_options.txt
........\.........\stdout.log
........\.........\syntmp
........\.........\......\TOP_UART.plg
........\.........\TOP_UART.areasrr
........\.........\TOP_UART.edn
........\.........\TOP_UART.map
........\.........\TOP_UART.pdc
........\.........\TOP_UART.sdf
........\.........\TOP_UART.so
........\.........\TOP_UART.srd
........\.........\TOP_UART.srm
........\.........\TOP_UART.srr
........\.........\TOP_UART.srs
........\.........\TOP_UART.szr
........\.........\TOP_UART.tlg
........\.........\TOP_UART_sdc.sdc
........\.........\TOP_UART_syn.prd
........\.........\TOP_UART_syn.prj
........\.........\traplog.tlg
........\top_uart.prj
........\viewdraw
........\........\sch
........\........\sym
........\........\vf
........\........\..\project.lst
........\........\viewdraw.ini
........\........\wir
TOP_UART.pdb

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