16-Channel, DDR LVDS Interface with Real-Time Window Monitoring

readme.txt
VERILOG
.......\BIT_ALIGN_MACHINE.v
.......\DDR_6TO1_16CHAN_RT_RX.v
.......\DDR_6TO1_16CHAN_RT_TX.v
.......\RESOURCE_SHARING_CONTROL.v
.......\RT_WINDOW_MONITOR.v
VHDL
....\BIT_ALIGN_MACHINE.vhd
....\count_to_128.vhd
....\count_to_16x.vhd
....\COUNT_TO_64.vhd
....\DDR_6TO1_16CHAN_RT_RX.vhd
....\DDR_6TO1_16CHAN_RT_TX.vhd
....\RESOURCE_SHARING_CONTROL.vhd
....\RT_WINDOW_MONITOR.vhd
....\seven_bit_reg_w_ce.vhd
xapp860.pdf

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