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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 99kb
  • Downloaded :0次
  • Author :聂***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
A simple paragraph of the core test code has been adopted to verify, VLOGER prepared
Packet file list
(Preview for download)
seg7led
.......\int_div.bsf
.......\int_div.v
.......\lpm_constant0.bsf
.......\lpm_constant0.cmp
.......\lpm_constant0.v
.......\lpm_constant0_bb.v
.......\lpm_counter0.bsf
.......\lpm_counter0.cmp
.......\lpm_counter0.v
.......\lpm_counter0_bb.v

.......\lpm_counter0_waveforms.html
.......\seg7led.asm.rpt
.......\seg7led.bdf
.......\seg7led.cdf
.......\seg7led.done
.......\seg7led.dpf
.......\seg7led.fit.rpt
.......\seg7led.fit.smsg
.......\seg7led.fit.summary
.......\seg7led.flow.rpt
.......\seg7led.map.rpt
.......\seg7led.map.smsg
.......\seg7led.map.summary
.......\seg7led.pin
.......\seg7led.pof
.......\seg7led.qpf
.......\seg7led.qsf
.......\seg7led.qws
.......\seg7led.sim.rpt
.......\seg7led.sof
.......\seg7led.tan.rpt
.......\seg7led.tan.summary
.......\seg7led.vwf
.......\seg7led_assignment_defaults.qdf
.......\segmain.bsf
.......\segmain.v
.......\segmain.v.bak
.......\segmain.vhd.bak
.......\setup.tcl
.......\setup.tcl.bak
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