VERILOG language with the digital phase-locked loop PLL

pll
...\cmp_state.ini
...\cnt10.v
...\db
...\..\pll_test.asm.qmsg
...\..\pll_test.cbx.xml
...\..\pll_test.cmp.cdb
...\..\pll_test.cmp.hdb
...\..\pll_test.cmp.rdb
...\..\pll_test.cmp.tdb
...\..\pll_test.cmp0.ddb
...\..\pll_test.db_info
...\..\pll_test.eco.cdb
...\..\pll_test.fit.qmsg
...\..\pll_test.hier_info
...\..\pll_test.hif
...\..\pll_test.map.cdb
...\..\pll_test.map.hdb
...\..\pll_test.map.qmsg
...\..\pll_test.pre_map.cdb
...\..\pll_test.pre_map.hdb
...\..\pll_test.psp
...\..\pll_test.rtlv.hdb
...\..\pll_test.rtlv_sg.cdb
...\..\pll_test.rtlv_sg_swap.cdb
...\..\pll_test.sgdiff.cdb
...\..\pll_test.sgdiff.hdb
...\..\pll_test.signalprobe.cdb
...\..\pll_test.sld_design_entry.sci
...\..\pll_test.sld_design_entry_dsc.sci
...\..\pll_test.syn_hier_info
...\..\pll_test.tan.qmsg
...\..\pll_test_cmp.qrpt
...\freqtest.v
...\pll.bsf
...\pll.v
...\pll_inst.v
...\pll_test.asm.rpt
...\pll_test.cdf
...\pll_test.done
...\pll_test.fit.eqn
...\pll_test.fit.rpt
...\pll_test.fit.summary
...\pll_test.flow.rpt
...\pll_test.map.eqn
...\pll_test.map.rpt
...\pll_test.map.summary
...\pll_test.pin
...\pll_test.pof
...\pll_test.qpf
...\pll_test.qsf
...\pll_test.qws
...\pll_test.sof
...\pll_test.tan.rpt
...\pll_test.tan.summary
...\pll_test.v
...\scan_led.v

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