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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.78mb
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  • Author :ch***
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Introduction - If you have any usage issues, please Google them yourself
direct digital frequency synthesis based on spartan-3e kitboard
Packet file list
(Preview for download)
MY_DDS
......\.lso
......\dac_summary.html
......\device_usage_statistics.html
......\div.prj
......\div.stx
......\div.vhd
......\div.xst
......\div_tbw.ant
......\div_tbw.jhd
......\div_tbw.tbw
......\div_tbw.vhw
......\div_tbw.xwv
......\div_tbw.xwv_bak
......\div_tbw_beh.prj
......\div_tbw_bencher.prj
......\div_tbw_isim_beh.exe
......\div_tbw_isim_beh.wfs
......\div_vhdl.prj
......\isim
......\....\file graph
......\....\temp
......\....\....\hdllib.ref
......\....\....\hdpdeps.ref
......\....\....\sub00
......\....\....\.....\vhpl00.vho
......\....\....\.....\vhpl01.vho
......\....\....\.....\vhpl02.vho
......\....\....\.....\vhpl03.vho
......\....\....\.....\vhpl04.vho
......\....\....\.....\vhpl05.vho
......\....\....\.....\vhpl06.vho
......\....\....\.....\vhpl07.vho
......\....\....\.....\vhpl08.vho
......\....\....\.....\vhpl09.vho
......\....\....\.....\vhpl10.vho
......\....\....\.....\vhpl11.vho
......\....\....\.....\vhpl12.vho
......\....\....\.....\vhpl13.vho
......\....\....\.....\vhpl14.vho
......\....\....\.....\vhpl15.vho
......\....\unisim.auxlib
......\....\.............\bufg
......\....\.............\....\bufg_v.h
......\....\.............\....\mingw
......\....\.............\....\.....\bufg_v.obj
......\....\.............\dcm_sp
......\....\.............\......\dcm_sp_v.h
......\....\.............\......\mingw
......\....\.............\......\.....\dcm_sp_v.obj
......\....\.............\dcm_sp_clock_divide_by_2
......\....\.............\........................\dcm_sp_clock_divide_by_2_v.h
......\....\.............\........................\mingw
......\....\.............\........................\.....\dcm_sp_clock_divide_by_2_v.obj
......\....\.............\dcm_sp_clock_lost
......\....\.............\.................\dcm_sp_clock_lost_v.h
......\....\.............\.................\mingw
......\....\.............\.................\.....\dcm_sp_clock_lost_v.obj
......\....\.............\dcm_sp_maximum_period_check
......\....\.............\...........................\dcm_sp_maximum_period_check_v.h
......\....\.............\...........................\mingw
......\....\.............\...........................\.....\dcm_sp_maximum_period_check_v.obj
......\....\.............\hdllib.ref
......\....\.............\ibufg
......\....\.............\.....\ibufg_v.h
......\....\.............\.....\mingw
......\....\.............\.....\.....\ibufg_v.obj
......\....\.............\vcomponents
......\....\.............\...........\mingw
......\....\.............\...........\.....\vcomponents.obj
......\....\.............\...........\vcomponents.h
......\....\.............\vpkg
......\....\.............\....\mingw
......\....\.............\....\.....\vpkg.obj
......\....\.............\....\vpkg.h
......\....\work
......\....\....\dac
......\....\....\...\behavioral.h
......\....\....\...\mingw
......\....\....\...\.....\behavioral.obj
......\....\....\div
......\....\....\...\behavioral.h
......\....\....\...\mingw
......\....\....\...\.....\behavioral.obj
......\....\....\div_tbw
......\....\....\.......\mingw
......\....\....\.......\.....\testbench_arch.obj
......\....\....\.......\testbench_arch.h
......\....\....\.......\xsimtestbench_arch.cpp
......\....\....\hdllib.ref
......\....\....\hdpdeps.ref
......\....\....\left_right_leds
......\....\....\...............\behavioral.h
......\....\....\...............\mingw
......\....\....\...............\.....\behavioral.obj
......\....\....\mydcm
......\....\....\.....\behavioral.h
......\....\....\.....\mingw
......\....\....\.....\.....\behavioral.obj
......\....\....\rg
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