FPGA module works, ADC0809 control state machine can be used directly ADC0809_VHDL_QUAARTUSII_PROJECT!

ADC0809控制
...........\ADC0809.bdf
...........\ADC0809.done
...........\ADC0809.flow.rpt
...........\ADC0809.map.rpt
...........\ADC0809.map.summary
...........\ADC0809.qpf
...........\ADC0809.qsf
...........\ADC0809.qws
...........\ADC0809VHDL.bsf
...........\ADC0809VHDL.vhd
...........\ADC0809VHDL.vhd.bak
...........\db
...........\..\ADC0809.cbx.xml
...........\..\ADC0809.cmp.rdb
...........\..\ADC0809.db_info
...........\..\ADC0809.eco.cdb
...........\..\ADC0809.hier_info
...........\..\ADC0809.hif
...........\..\ADC0809.map.bpm
...........\..\ADC0809.map.cdb
...........\..\ADC0809.map.ecobp
...........\..\ADC0809.map.hdb
...........\..\ADC0809.map.logdb
...........\..\ADC0809.map.qmsg
...........\..\ADC0809.map_bb.cdb
...........\..\ADC0809.map_bb.hdb
...........\..\ADC0809.map_bb.hdbx
...........\..\ADC0809.map_bb.logdb
...........\..\ADC0809.pre_map.cdb
...........\..\ADC0809.pre_map.hdb
...........\..\ADC0809.psp
...........\..\ADC0809.root_partition.map.atm
...........\..\ADC0809.root_partition.map.hdbx
...........\..\ADC0809.root_partition.map.info
...........\..\ADC0809.rtlv.hdb
...........\..\ADC0809.rtlv_sg.cdb
...........\..\ADC0809.rtlv_sg_swap.cdb
...........\..\ADC0809.sgdiff.cdb
...........\..\ADC0809.sgdiff.hdb
...........\..\ADC0809.sld_design_entry.sci
...........\..\ADC0809.sld_design_entry_dsc.sci
...........\..\ADC0809.smp_dump.txt
...........\..\ADC0809.syn_hier_info
...........\..\ADC0809.tis_db_list.ddb
...........\..\prev_cmp_ADC0809.qmsg

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