Verilog language programming to the use of FPGA development tools for the realization of digital tube 0-3 show!

shuma0-3
........\component
........\constraint
........\coreconsole
........\designer
........\........\impl1
........\........\.....\designer.log
........\........\.....\ledtest.adb
........\........\.....\ledtest.dtf
........\........\.....\...........\verify.log
........\........\.....\ledtest.ide_des
........\........\.....\ledtest.pdb
........\........\.....\ledtest.pdb.depends
........\........\.....\ledtest.tcl
........\........\.....\ledtest_fp
........\........\.....\..........\$$FlashPro_FPBBALTLPT1.L$$
........\........\.....\..........\ledtest.log
........\........\.....\..........\ledtest.pro
........\........\.....\..........\projectData
........\........\.....\..........\...........\ledtest.pdb
........\........\.....\simulation
........\hdl
........\...\ledtest.v
........\ledtest.prj
........\phy_synthesis
........\simulation
........\..........\modelsim.ini
........\..........\modelsim.ini.sav
........\smartgen
........\........\smartgen.aws
........\stimulus
........\synthesis
........\.........\.recordref
........\.........\backup
........\.........\......\ledtest.srr
........\.........\coreip
........\.........\ledtest.areasrr
........\.........\ledtest.edn
........\.........\ledtest.map
........\.........\ledtest.sdf
........\.........\ledtest.so
........\.........\ledtest.srd
........\.........\ledtest.srm
........\.........\ledtest.srr
........\.........\ledtest.srs
........\.........\ledtest.tlg
........\.........\ledtest_sdc.sdc
........\.........\ledtest_syn.prd
........\.........\ledtest_syn.prj
........\.........\run_options.txt
........\.........\stdout.log
........\.........\syntmp
........\.........\......\ledtest.msg
........\.........\......\ledtest.plg
........\.........\traplog.tlg
........\viewdraw
........\........\sch
........\........\sym
........\........\vf
........\........\..\project.lst
........\........\viewdraw.ini
........\........\wir

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