The Verilog bidirectional RAM process, to achieve a two-way mass data

in_out_put
..........\data_source.v
..........\db
..........\..\altsyncram_47m1.tdf
..........\..\altsyncram_96o1.tdf
..........\..\altsyncram_jvf1.tdf
..........\..\altsyncram_lij1.tdf
..........\..\in_out_put.asm.qmsg
..........\..\in_out_put.asm_labs.ddb
..........\..\in_out_put.cbx.xml
..........\..\in_out_put.cmp.bpm
..........\..\in_out_put.cmp.cdb
..........\..\in_out_put.cmp.ecobp
..........\..\in_out_put.cmp.hdb
..........\..\in_out_put.cmp.logdb
..........\..\in_out_put.cmp.rdb
..........\..\in_out_put.cmp.tdb
..........\..\in_out_put.cmp0.ddb
..........\..\in_out_put.cmp2.ddb
..........\..\in_out_put.cmp_bb.cdb
..........\..\in_out_put.cmp_bb.hdb
..........\..\in_out_put.cmp_bb.logdb
..........\..\in_out_put.cmp_bb.rcf
..........\..\in_out_put.dbp
..........\..\in_out_put.db_info
..........\..\in_out_put.eco.cdb
..........\..\in_out_put.eds_overflow
..........\..\in_out_put.fit.qmsg
..........\..\in_out_put.fnsim.cdb
..........\..\in_out_put.fnsim.hdb
..........\..\in_out_put.fnsim.qmsg
..........\..\in_out_put.hier_info
..........\..\in_out_put.hif
..........\..\in_out_put.map.bpm
..........\..\in_out_put.map.cdb
..........\..\in_out_put.map.ecobp
..........\..\in_out_put.map.hdb
..........\..\in_out_put.map.logdb
..........\..\in_out_put.map.qmsg
..........\..\in_out_put.map_bb.cdb
..........\..\in_out_put.map_bb.hdb
..........\..\in_out_put.map_bb.logdb
..........\..\in_out_put.pre_map.cdb
..........\..\in_out_put.pre_map.hdb
..........\..\in_out_put.psp
..........\..\in_out_put.pss
..........\..\in_out_put.rpp.qmsg
..........\..\in_out_put.rtlv.hdb
..........\..\in_out_put.rtlv_sg.cdb
..........\..\in_out_put.rtlv_sg_swap.cdb
..........\..\in_out_put.sgate.rvd
..........\..\in_out_put.sgate_sm.rvd
..........\..\in_out_put.sgdiff.cdb
..........\..\in_out_put.sgdiff.hdb
..........\..\in_out_put.signalprobe.cdb
..........\..\in_out_put.sim.cvwf
..........\..\in_out_put.sim.hdb
..........\..\in_out_put.sim.qmsg
..........\..\in_out_put.sim.rdb
..........\..\in_out_put.simfam
..........\..\in_out_put.sld_design_entry.sci
..........\..\in_out_put.sld_design_entry_dsc.sci
..........\..\in_out_put.smp_dump.txt
..........\..\in_out_put.syn_hier_info
..........\..\in_out_put.tan.qmsg
..........\..\in_out_put.tis_db_list.ddb
..........\..\prev_cmp_in_out_put.asm.qmsg
..........\..\prev_cmp_in_out_put.fit.qmsg
..........\..\prev_cmp_in_out_put.map.qmsg
..........\..\prev_cmp_in_out_put.qmsg
..........\..\prev_cmp_in_out_put.sim.qmsg
..........\..\prev_cmp_in_out_put.tan.qmsg
..........\..\wed.wsf
..........\DUALRAM.v
..........\dualram1.v
..........\in_out_put.asm.rpt
..........\in_out_put.done
..........\in_out_put.fit.rpt
..........\in_out_put.fit.smsg
..........\in_out_put.fit.summary
..........\in_out_put.flow.rpt
..........\in_out_put.map.rpt
..........\in_out_put.map.smsg
..........\in_out_put.map.summary
..........\in_out_put.pin
..........\in_out_put.pof
..........\in_out_put.qpf
..........\in_out_put.qsf
..........\in_out_put.sim.rpt
..........\in_out_put.sof
..........\in_out_put.tan.rpt
..........\in_out_put.tan.summary
..........\in_out_put.v
..........\in_out_put.v.bak
..........\in_out_put.vwf
..........\wr_counter.v
..........\wr_counter.v.bak
..........\wr_counter1.v

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