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DEMO_45_RAM

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 937kb
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  • Author :fuc***
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Introduction - If you have any usage issues, please Google them yourself
This is the description of a ram in vhdl language it beautiful
Packet file list
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DEMO_45_RAM
...........\5_RAM.MIF
...........\cmp_state.ini
...........\DB
...........\..\altsyncram_4qb1.tdf
...........\..\altsyncram_9gm2.tdf
...........\..\decode_ogi.tdf
...........\..\RAM_DP1.asm.qmsg
...........\..\RAM_DP1.cbx.xml
...........\..\RAM_DP1.cmp.cdb
...........\..\RAM_DP1.cmp.hdb
...........\..\RAM_DP1.cmp.kpt
...........\..\RAM_DP1.cmp.logdb
...........\..\RAM_DP1.cmp.rdb
...........\..\RAM_DP1.cmp.tdb
...........\..\RAM_DP1.cmp0.ddb
...........\..\RAM_DP1.dbp
...........\..\RAM_DP1.db_info
...........\..\RAM_DP1.eco.cdb
...........\..\RAM_DP1.fit.qmsg
...........\..\RAM_DP1.hier_info
...........\..\RAM_DP1.hif
...........\..\RAM_DP1.map.cdb
...........\..\RAM_DP1.map.hdb
...........\..\RAM_DP1.map.logdb
...........\..\RAM_DP1.map.qmsg
...........\..\RAM_DP1.pre_map.cdb
...........\..\RAM_DP1.pre_map.hdb
...........\..\RAM_DP1.psp
...........\..\RAM_DP1.rtlv.hdb
...........\..\RAM_DP1.rtlv_sg.cdb
...........\..\RAM_DP1.rtlv_sg_swap.cdb
...........\..\RAM_DP1.sgdiff.cdb
...........\..\RAM_DP1.sgdiff.hdb
...........\..\RAM_DP1.signalprobe.cdb
...........\..\RAM_DP1.sld_design_entry.sci
...........\..\RAM_DP1.sld_design_entry_dsc.sci
...........\..\RAM_DP1.syn_hier_info
...........\..\RAM_DP1.tan.qmsg
...........\FITFSTIO.TXT
...........\RAM_DP.GDF
...........\RAM_DP1.ACF
...........\RAM_DP1.asm.rpt
...........\RAM_DP1.BDF
...........\RAM_DP1.CDF
...........\RAM_DP1.done
...........\RAM_DP1.dpf
...........\RAM_DP1.FIT
...........\RAM_DP1.fit.rpt
...........\RAM_DP1.fit.smsg
...........\RAM_DP1.fit.summary
...........\RAM_DP1.flow.rpt
...........\RAM_DP1.HIF
...........\RAM_DP1.map.rpt
...........\RAM_DP1.map.summary
...........\RAM_DP1.MIF
...........\RAM_DP1.MMF
...........\RAM_DP1.NDB
...........\RAM_DP1.PIN
...........\RAM_DP1.pof
...........\RAM_DP1.QPF
...........\RAM_DP1.QSF
...........\RAM_DP1.QWS
...........\RAM_DP1.SNF
...........\RAM_DP1.SOF
...........\RAM_DP1.tan.rpt
...........\RAM_DP1.tan.summary
...........\RAM_DP1_assignment_defaults.qdf
...........\RAM_DQ0.BSF
...........\RAM_DQ0.VHD
...........\实验3_2.pdf
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