Verilog prepared by the project, has passed through the serial debug debugging assistant, receiving 8 times the baud rate module sampling data, a better filtering in the PC to complete the voluntary self-close feature.

uart控制器
..........\tx波形.doc
..........\uart_rx
..........\.......\db
..........\.......\..\uart_rx.asm.qmsg
..........\.......\..\uart_rx.cbx.xml
..........\.......\..\uart_rx.cmp.cdb
..........\.......\..\uart_rx.cmp.hdb
..........\.......\..\uart_rx.cmp.kpt
..........\.......\..\uart_rx.cmp.logdb
..........\.......\..\uart_rx.cmp.rdb
..........\.......\..\uart_rx.cmp.tdb
..........\.......\..\uart_rx.cmp0.ddb
..........\.......\..\uart_rx.dbp
..........\.......\..\uart_rx.db_info
..........\.......\..\uart_rx.eco.cdb
..........\.......\..\uart_rx.eda.qmsg
..........\.......\..\uart_rx.eds_overflow
..........\.......\..\uart_rx.fit.qmsg
..........\.......\..\uart_rx.hier_info
..........\.......\..\uart_rx.hif
..........\.......\..\uart_rx.map.cdb
..........\.......\..\uart_rx.map.hdb
..........\.......\..\uart_rx.map.logdb
..........\.......\..\uart_rx.map.qmsg
..........\.......\..\uart_rx.pre_map.cdb
..........\.......\..\uart_rx.pre_map.hdb
..........\.......\..\uart_rx.psp
..........\.......\..\uart_rx.rtlv.hdb
..........\.......\..\uart_rx.rtlv_sg.cdb
..........\.......\..\uart_rx.rtlv_sg_swap.cdb
..........\.......\..\uart_rx.sgdiff.cdb
..........\.......\..\uart_rx.sgdiff.hdb
..........\.......\..\uart_rx.signalprobe.cdb
..........\.......\..\uart_rx.sim.hdb
..........\.......\..\uart_rx.sim.qmsg
..........\.......\..\uart_rx.sim.rdb
..........\.......\..\uart_rx.sim.vwf
..........\.......\..\uart_rx.sld_design_entry.sci
..........\.......\..\uart_rx.sld_design_entry_dsc.sci
..........\.......\..\uart_rx.smp_dump.txt
..........\.......\..\uart_rx.syn_hier_info
..........\.......\..\uart_rx.tan.qmsg
..........\.......\..\wed.zsf
..........\.......\simulation
..........\.......\..........\activehdl
..........\.......\..........\.........\uart_rx.vo
..........\.......\..........\.........\uart_rx_v.sdo
..........\.......\timing
..........\.......\......\primetime
..........\.......\......\.........\uart_rx.vho
..........\.......\......\.........\uart_rx_pt_vhd.tcl
..........\.......\......\.........\uart_rx_vhd.sdo
..........\.......\uart_rx.asm.rpt
..........\.......\uart_rx.cdf
..........\.......\uart_rx.done
..........\.......\uart_rx.dpf
..........\.......\uart_rx.eda.rpt
..........\.......\uart_rx.fit.rpt
..........\.......\uart_rx.fit.smsg
..........\.......\uart_rx.fit.summary
..........\.......\uart_rx.flow.rpt
..........\.......\uart_rx.map.rpt
..........\.......\uart_rx.map.smsg
..........\.......\uart_rx.map.summary
..........\.......\uart_rx.pin
..........\.......\uart_rx.pof
..........\.......\uart_rx.qpf
..........\.......\uart_rx.qsf
..........\.......\uart_rx.qws
..........\.......\uart_rx.sim.rpt
..........\.......\uart_rx.sof
..........\.......\uart_rx.tan.rpt
..........\.......\uart_rx.tan.summary
..........\.......\uart_rx.v
..........\.......\uart_rx.vwf
..........\uart_top
..........\........\db
..........\........\..\uart_top.asm.qmsg
..........\........\..\uart_top.cbx.xml
..........\........\..\uart_top.cmp.cdb
..........\........\..\uart_top.cmp.hdb
..........\........\..\uart_top.cmp.kpt
..........\........\..\uart_top.cmp.logdb
..........\........\..\uart_top.cmp.rdb
..........\........\..\uart_top.cmp.tdb
..........\........\..\uart_top.cmp0.ddb
..........\........\..\uart_top.dbp
..........\........\..\uart_top.db_info
..........\........\..\uart_top.eco.cdb
..........\........\..\uart_top.eda.qmsg
..........\........\..\uart_top.eds_overflow
..........\........\..\uart_top.fit.qmsg
..........\........\..\uart_top.hier_info
..........\........\..\uart_top.hif
..........\........\..\uart_top.map.cdb
..........\........\..\uart_top.map.hdb
..........\........\..\uart_top.map.logdb
..........\........\..\uart_top.map.qmsg
..........\........\..\uart_top.pre_map.cdb

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