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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 507kb
  • Downloaded :0次
  • Author :林***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Their written, based on instruments used in verilog addition and subtraction! ! ! Is relatively simple! !
Packet file list
(Preview for download)
as
..\as.asm.rpt
..\as.bdf
..\as.cdf
..\as.done
..\as.dpf
..\as.fit.rpt
..\as.fit.smsg
..\as.fit.summary
..\as.flow.rpt
..\as.map.rpt
..\as.map.summary
..\as.pin
..\as.pof
..\as.qpf
..\as.qsf
..\as.qws
..\as.sof
..\as.tan.rpt
..\as.tan.summary
..\a_s.bsf
..\a_s.v
..\a_s.v.bak
..\db
..\..\as.asm.qmsg
..\..\as.asm_labs.ddb
..\..\as.cbx.xml
..\..\as.cmp.cdb
..\..\as.cmp.ecobp
..\..\as.cmp.hdb
..\..\as.cmp.logdb
..\..\as.cmp.rdb
..\..\as.cmp.tdb
..\..\as.cmp0.ddb
..\..\as.cmp2.ddb
..\..\as.db_info
..\..\as.eco.cdb
..\..\as.fit.qmsg
..\..\as.hier_info
..\..\as.hif
..\..\as.map.cdb
..\..\as.map.ecobp
..\..\as.map.hdb
..\..\as.map.logdb
..\..\as.map.qmsg
..\..\as.map_bb.hdbx
..\..\as.map_bb.logdb
..\..\as.pre_map.cdb
..\..\as.pre_map.hdb
..\..\as.psp
..\..\as.root_partition.cmp.atm
..\..\as.root_partition.cmp.dfp
..\..\as.root_partition.cmp.hdbx
..\..\as.root_partition.cmp.logdb
..\..\as.root_partition.cmp.rcf
..\..\as.root_partition.map.atm
..\..\as.root_partition.map.hdbx
..\..\as.root_partition.map.info
..\..\as.rtlv.hdb
..\..\as.rtlv_sg.cdb
..\..\as.rtlv_sg_swap.cdb
..\..\as.sgdiff.cdb
..\..\as.sgdiff.hdb
..\..\as.signalprobe.cdb
..\..\as.sld_design_entry.sci
..\..\as.sld_design_entry_dsc.sci
..\..\as.smp_dump.txt
..\..\as.syn_hier_info
..\..\as.tan.qmsg
..\..\as.tis_db_list.ddb
..\..\as.tmw_info
..\..\prev_cmp_as.asm.qmsg
..\..\prev_cmp_as.fit.qmsg
..\..\prev_cmp_as.map.qmsg
..\..\prev_cmp_as.qmsg
..\..\prev_cmp_as.tan.qmsg
..\key.bsf
..\key.v
..\key.v.bak
..\seg.v
..\seg4_8.bsf
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