Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification

mutiplier


.........\adder8b.bsf
.........\adder8b.vhd
.........\adder8b.vwf

.........\andarith.bsf
.........\andarith.vhd
.........\andarith.vwf

.........\arictl.bsf
.........\arictl.vhd
.........\arictl.vwf
.........\cmp_state.ini
.........\db
.........\..\sreg8b.asm.qmsg
.........\..\sreg8b.cbx.xml
.........\..\sreg8b.cmp.cdb
.........\..\sreg8b.cmp.hdb
.........\..\sreg8b.cmp.rdb
.........\..\sreg8b.cmp.tdb
.........\..\sreg8b.cmp0.ddb
.........\..\sreg8b.db_info
.........\..\sreg8b.eco.cdb
.........\..\sreg8b.eds_overflow
.........\..\sreg8b.fit.qmsg
.........\..\sreg8b.hier_info
.........\..\sreg8b.hif
.........\..\sreg8b.map.cdb
.........\..\sreg8b.map.hdb
.........\..\sreg8b.map.qmsg
.........\..\sreg8b.pre_map.cdb
.........\..\sreg8b.pre_map.hdb
.........\..\sreg8b.psp
.........\..\sreg8b.rtlv.hdb
.........\..\sreg8b.rtlv_sg.cdb
.........\..\sreg8b.rtlv_sg_swap.cdb
.........\..\sreg8b.sgdiff.cdb
.........\..\sreg8b.sgdiff.hdb
.........\..\sreg8b.signalprobe.cdb
.........\..\sreg8b.sim.hdb
.........\..\sreg8b.sim.qmsg
.........\..\sreg8b.sim.rdb
.........\..\sreg8b.sim.vwf
.........\..\sreg8b.sld_design_entry.sci
.........\..\sreg8b.sld_design_entry_dsc.sci
.........\..\sreg8b.syn_hier_info
.........\..\sreg8b.tan.qmsg
.........\..\sreg8b_cmp.qrpt
.........\..\sreg8b_sim.qrpt
.........\multi8x8.bdf
.........\multi8x8.vwf

.........\reg16b.bsf
.........\reg16b.vhd
.........\reg16b.vwf
.........\sreg8b.asm.rpt
.........\sreg8b.bsf
.........\sreg8b.done
.........\sreg8b.fit.eqn
.........\sreg8b.fit.rpt
.........\sreg8b.fit.summary
.........\sreg8b.flow.rpt
.........\sreg8b.map.eqn
.........\sreg8b.map.rpt
.........\sreg8b.map.summary
.........\sreg8b.pin
.........\sreg8b.pof
.........\sreg8b.qpf
.........\sreg8b.qsf
.........\sreg8b.qws
.........\sreg8b.sim.rpt
.........\sreg8b.sof
.........\sreg8b.tan.rpt
.........\sreg8b.tan.summary
.........\sreg8b.vhd
.........\sreg8b.vwf

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