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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 10.93mb
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  • Author :戚***
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Introduction - If you have any usage issues, please Google them yourself
quartus_nios comprehensive development platform that can interrupt more important is that it' s cpu can operate at 150M, bus work in 100M × 32bit
Packet file list
(Preview for download)
150M
....\adapter_downstream_pipeline_0.vhd
....\adapter_downstream_pipeline_1.vhd
....\adapter_downstream_pipeline_2.vhd
....\adapter_downstream_pipeline_3.vhd
....\adapter_downstream_pipeline_4.vhd
....\adapter_downstream_pipeline_5.vhd
....\adapter_downstream_pipeline_6.vhd
....\adapter_slave_y_0.vhd
....\adapter_slave_y_1.vhd
....\adapter_waitrequest_pipeline_0.vhd
....\adapter_waitrequest_pipeline_1.vhd
....\adapter_waitrequest_pipeline_2.vhd
....\adapter_waitrequest_pipeline_3.vhd
....\adapter_waitrequest_pipeline_4.vhd
....\adapter_waitrequest_pipeline_5.vhd
....\adapter_waitrequest_pipeline_6.vhd
....\adapter_waitrequest_pipeline_7.vhd
....\adapter_waitrequest_pipeline_8.vhd
....\altera_vhdl_support.vhd
....\altpllpll.bsf
....\altpllpll.cmp
....\altpllpll.ppf
....\altpllpll.vhd
....\altpllpll_0.bsf
....\altpllpll_0.cmp
....\altpllpll_0.ppf
....\altpllpll_0.vhd
....\altpllpll_0_inst.vhd

....\altpllpll_0_waveforms.html
....\altpllpll_inst.vhd

....\altpllpll_waveforms.html
....\button.vhd
....\button_test.asm.rpt
....\button_test.bdf
....\button_test.cdf
....\button_test.done
....\button_test.fit.eqn
....\button_test.fit.rpt
....\button_test.fit.smsg
....\button_test.fit.summary
....\button_test.flow.rpt
....\button_test.jdi
....\button_test.map.eqn
....\button_test.map.rpt
....\button_test.map.summary
....\button_test.pin
....\button_test.pof
....\button_test.qpf
....\button_test.qsf
....\button_test.qws
....\button_test.sdc
....\button_test.sof
....\button_test.tan.rpt
....\button_test.tan.summary
....\button_test_assignment_defaults.qdf
....\Chain1.cdf
....\clock_0.vhd
....\clock_1.vhd
....\clock_2.vhd
....\clock_3.vhd
....\clock_4.vhd
....\clock_5.vhd
....\clock_6.vhd
....\clock_7.vhd
....\cpu.ocp
....\cpu.vhd
....\cpu_ic_tag_ram.mif
....\cpu_jtag_debug_module.vhd
....\cpu_jtag_debug_module_wrapper.vhd
....\cpu_ociram_default_contents.mif
....\cpu_rf_ram_a.mif
....\cpu_rf_ram_b.mif
....\cpu_test_bench.vhd
....\db
....\..\add_sub_pjg.tdf
....\..\altsyncram_3171.tdf
....\..\altsyncram_9tl1.tdf
....\..\altsyncram_ak41.tdf
....\..\altsyncram_bhc1.tdf
....\..\altsyncram_cf61.tdf
....\..\altsyncram_cro1.tdf
....\..\altsyncram_cub1.tdf
....\..\altsyncram_df61.tdf
....\..\altsyncram_duv1.tdf
....\..\altsyncram_e502.tdf
....\..\altsyncram_hp61.tdf
....\..\altsyncram_k1l1.tdf
....\..\altsyncram_l6e1.tdf
....\..\altsyncram_m6e1.tdf
....\..\altsyncram_qge1.tdf
....\..\altsyncram_rmv1.tdf
....\..\altsyncram_sr41.tdf
....\..\altsyncram_t072.tdf
....\..\altsyncram_toc1.tdf
....\..\altsyncram_u2p1.tdf
....\..\altsyncram_um61.tdf
....\..\altsyncram_vfb1.tdf
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