verilog fpga

S1_38yima
.........\proj
.........\....\cmp_state.ini
.........\....\db
.........\....\..\yiamqi.db_info
.........\....\..\yiamqi.eco.cdb
.........\....\..\yiamqi.sld_design_entry.sci
.........\....\..\yiamqi_cmp.qrpt
.........\....\..\yiamqi_sim.qrpt
.........\....\translater.v
.........\....\Waveform1.vwf
.........\....\yiamqi.asm.rpt
.........\....\yiamqi.cdf
.........\....\yiamqi.done
.........\....\yiamqi.dpf
.........\....\yiamqi.eda.rpt
.........\....\yiamqi.fit.eqn
.........\....\yiamqi.fit.rpt
.........\....\yiamqi.fit.smsg
.........\....\yiamqi.fit.summary
.........\....\yiamqi.flow.rpt
.........\....\yiamqi.map.eqn
.........\....\yiamqi.map.rpt
.........\....\yiamqi.map.summary
.........\....\yiamqi.pin
.........\....\yiamqi.pof
.........\....\yiamqi.ppl
.........\....\yiamqi.qpf
.........\....\yiamqi.qsf
.........\....\yiamqi.qws
.........\....\yiamqi.sim.rpt
.........\....\yiamqi.sof
.........\....\yiamqi.tan.rpt
.........\....\yiamqi.tan.summary
.........\....\yiamqi.vwf
.........\....\yiamqi_assignment_defaults.qdf
.........\....\yiamqi_description.txt
.........\说明.txt

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