The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES

TX
..\db
..\..\TX.asm.qmsg
..\..\TX.cbx.xml
..\..\TX.cmp.rdb
..\..\TX.dbp
..\..\TX.db_info
..\..\TX.eco.cdb
..\..\TX.eds_overflow
..\..\TX.fit.qmsg
..\..\TX.hier_info
..\..\TX.hif
..\..\TX.map.cdb
..\..\TX.map.hdb
..\..\TX.map.logdb
..\..\TX.map.qmsg
..\..\TX.pre_map.cdb
..\..\TX.pre_map.hdb
..\..\TX.psp
..\..\TX.pss
..\..\TX.rpp.qmsg
..\..\TX.rtlv.hdb
..\..\TX.rtlv_sg.cdb
..\..\TX.rtlv_sg_swap.cdb
..\..\TX.sgate.rvd
..\..\TX.sgate_sm.rvd
..\..\TX.sgdiff.cdb
..\..\TX.sgdiff.hdb
..\..\TX.sim.hdb
..\..\TX.sim.qmsg
..\..\TX.sim.rdb
..\..\TX.sim_ori.vwf
..\..\TX.sld_design_entry.sci
..\..\TX.sld_design_entry_dsc.sci
..\..\TX.syn_hier_info
..\..\TX.tan.qmsg
..\..\wed.zsf
..\EN_8B10B.bsf
..\en_8b10b.vhd
..\OTHER.vhd
..\TX.asm.rpt
..\TX.bdf
..\TX.done
..\TX.dpf
..\TX.fit.rpt
..\TX.fit.summary
..\TX.flow.rpt
..\TX.map.rpt
..\TX.map.summary
..\TX.pin
..\TX.pof
..\TX.qpf
..\TX.qsf
..\TX.qws
..\TX.sim.rpt
..\TX.tan.rpt
..\TX.tan.summary
..\TX.vwf

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