PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES

RX
..\db
..\..\RX.asm.qmsg
..\..\RX.cbx.xml
..\..\RX.cmp.rdb
..\..\RX.dbp
..\..\RX.db_info
..\..\RX.eco.cdb
..\..\RX.eds_overflow
..\..\RX.fit.qmsg
..\..\RX.hier_info
..\..\RX.hif
..\..\RX.map.cdb
..\..\RX.map.hdb
..\..\RX.map.logdb
..\..\RX.map.qmsg
..\..\RX.pre_map.cdb
..\..\RX.pre_map.hdb
..\..\RX.psp
..\..\RX.pss
..\..\RX.rpp.qmsg
..\..\RX.rtlv.hdb
..\..\RX.rtlv_sg.cdb
..\..\RX.rtlv_sg_swap.cdb
..\..\RX.sgate.rvd
..\..\RX.sgate_sm.rvd
..\..\RX.sgdiff.cdb
..\..\RX.sgdiff.hdb
..\..\RX.sim.hdb
..\..\RX.sim.qmsg
..\..\RX.sim.rdb
..\..\RX.sim_ori.vwf
..\..\RX.sld_design_entry.sci
..\..\RX.sld_design_entry_dsc.sci
..\..\RX.syn_hier_info
..\..\RX.tan.qmsg
..\..\wed.zsf
..\DE_8B10B.bsf
..\de_8b10b.vhd
..\OTHER.vhd
..\RX.asm.rpt
..\RX.bdf
..\RX.done
..\RX.fit.rpt
..\RX.fit.summary
..\RX.flow.rpt
..\RX.map.rpt
..\RX.map.summary
..\RX.pin
..\RX.pof
..\RX.qpf
..\RX.qsf
..\RX.qws
..\RX.sim.rpt
..\RX.tan.rpt
..\RX.tan.summary
..\RX.vwf

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