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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2012-11-26
- Size : 1kb
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Introduction - If you have any usage issues, please Google them yourself
Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test
Packet file list
(Preview for download)
HDB3.v
HDB3_tb.v
HDB3_tb.v
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