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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 204kb
  • Downloaded :0次
  • Author :周****
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fulladd
Packet file list
(Preview for download)
FullAdd
.......\db
.......\..\FullAdd.asm.qmsg
.......\..\FullAdd.asm_labs.ddb
.......\..\FullAdd.cbx.xml
.......\..\FullAdd.cmp.cdb
.......\..\FullAdd.cmp.hdb
.......\..\FullAdd.cmp.logdb
.......\..\FullAdd.cmp.qrpt
.......\..\FullAdd.cmp.rdb
.......\..\FullAdd.cmp.tdb
.......\..\FullAdd.cmp0.ddb
.......\..\FullAdd.cmp2.ddb
.......\..\FullAdd.dbp
.......\..\FullAdd.db_info
.......\..\FullAdd.eco.cdb
.......\..\FullAdd.fit.qmsg
.......\..\FullAdd.hier_info
.......\..\FullAdd.hif
.......\..\FullAdd.map.cdb
.......\..\FullAdd.map.hdb
.......\..\FullAdd.map.logdb
.......\..\FullAdd.map.qmsg
.......\..\FullAdd.pre_map.cdb
.......\..\FullAdd.pre_map.hdb
.......\..\FullAdd.psp
.......\..\FullAdd.rtlv.hdb
.......\..\FullAdd.rtlv_sg.cdb
.......\..\FullAdd.rtlv_sg_swap.cdb
.......\..\FullAdd.sgdiff.cdb
.......\..\FullAdd.sgdiff.hdb
.......\..\FullAdd.signalprobe.cdb
.......\..\FullAdd.sld_design_entry.sci
.......\..\FullAdd.sld_design_entry_dsc.sci
.......\..\FullAdd.syn_hier_info
.......\..\FullAdd.tan.qmsg
.......\FullAdd.asm.rpt
.......\FullAdd.bdf
.......\FullAdd.cdf
.......\FullAdd.done
.......\FullAdd.fit.eqn
.......\FullAdd.fit.rpt
.......\FullAdd.fit.summary
.......\FullAdd.flow.rpt
.......\FullAdd.map.eqn
.......\FullAdd.map.rpt
.......\FullAdd.map.summary
.......\FullAdd.pin
.......\FullAdd.pof
.......\FullAdd.qpf
.......\FullAdd.qsf
.......\FullAdd.qws
.......\FullAdd.sof
.......\FullAdd.tan.rpt
.......\FullAdd.tan.summary
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