Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve

cheng 1
.......\cheng
.......\.....\cheng.flow.rpt
.......\.....\cheng.map.rpt
.......\.....\cheng.map.summary
.......\.....\cheng.qpf
.......\.....\cheng.qsf
.......\.....\cheng.qws
.......\.....\cheng.vhd
.......\.....\db
.......\.....\..\cheng.cbx.xml
.......\.....\..\cheng.cmp.rdb
.......\.....\..\cheng.db_info
.......\.....\..\cheng.eco.cdb
.......\.....\..\cheng.map.qmsg
.......\.....\..\cheng.map_bb.hdb
.......\.....\..\cheng.map_bb.hdbx
.......\.....\..\cheng.sld_design_entry.sci
.......\.....\..\cheng.tis_db_list.ddb
.......\.....\..\prev_cmp_cheng.map.qmsg
.......\.....\..\prev_cmp_cheng.qmsg

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