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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 26kb
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  • Author :齐***
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Introduction - If you have any usage issues, please Google them yourself
Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
Packet file list
(Preview for download)
cheng 1
.......\cheng
.......\.....\cheng.flow.rpt
.......\.....\cheng.map.rpt
.......\.....\cheng.map.summary
.......\.....\cheng.qpf
.......\.....\cheng.qsf
.......\.....\cheng.qws
.......\.....\cheng.vhd
.......\.....\db
.......\.....\..\cheng.cbx.xml
.......\.....\..\cheng.cmp.rdb
.......\.....\..\cheng.db_info
.......\.....\..\cheng.eco.cdb
.......\.....\..\cheng.map.qmsg
.......\.....\..\cheng.map_bb.hdb
.......\.....\..\cheng.map_bb.hdbx
.......\.....\..\cheng.sld_design_entry.sci
.......\.....\..\cheng.tis_db_list.ddb
.......\.....\..\prev_cmp_cheng.map.qmsg
.......\.....\..\prev_cmp_cheng.qmsg
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