Fun little FPGA that plays a portion of Habanera

analog.v
bitgen.ut
clocks.bgn
clocks.bit
Clocks.bld
Clocks.cmd_log
clocks.drc
Clocks.lfp
Clocks.lso
Clocks.mrp
Clocks.nc1
Clocks.ncd
Clocks.ngc
Clocks.ngd
Clocks.ngm
Clocks.ngr
Clocks.pad
Clocks.pad_txt
Clocks.par
Clocks.pcf
Clocks.prj
Clocks.syr
Clocks.twr
Clocks.twx
Clocks.ucf
Clocks.ut
Clocks.v
Clocks.xpi
Clocks_clockTest_v_tf.fdo
Clocks_clockTest_v_tf.udo
Clocks_last_par.ncd
Clocks_map.ncd
Clocks_map.ngm
Clocks_pad.csv
Clocks_pad.txt
clockTest.v
habanera.bgn
habanera.bit
Habanera.bld
Habanera.cmd_log
habanera.drc
Habanera.lso
Habanera.mrp
Habanera.nc1
Habanera.ncd
Habanera.ngc
Habanera.ngd
Habanera.ngm
Habanera.ngr
Habanera.pad
Habanera.pad_txt
Habanera.par
Habanera.pcf
Habanera.prj
Habanera.syr
Habanera.twr
Habanera.twx
Habanera.ucf
Habanera.ut
Habanera.v
Habanera.xpi
Habanera_last_par.ncd
Habanera_map.ncd
Habanera_map.ngm
Habanera_pad.csv
Habanera_pad.txt
Habenera.dhp
Habenera.npl
notes
scale
Test.v
Test_v_tf.fdo
Test_v_tf.udo
ToneGenerator.dhp
ToneGenerator.npl
transcript
Vamp
vsim.wlf
wave.do
work
....\@as
....\...\verilog.psm
....\...\_primary.dat
....\...\_primary.vhd
....\@clocks
....\.......\verilog.psm
....\.......\_primary.dat
....\.......\_primary.vhd
....\@clocks_clock@test_v_tf
....\.......................\verilog.psm
....\.......................\_primary.dat
....\.......................\_primary.vhd
....\@controller
....\...........\verilog.psm
....\...........\_primary.dat
....\...........\_primary.vhd
....\@controller_@controller@test_v_tf
....\.................................\verilog.psm
....\.................................\_primary.dat
....\.................................\_primary.vhd

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