VHDL key

VHDL语言开发7279读写键盘程序
............................\Inter（629）
............................\............\altdpram0.vhd
............................\............\CLK_DIV.vhd
............................\............\cmp_state.ini
............................\............\connecter.bsf
............................\............\db
............................\............\..\add_sub_0nh.tdf
............................\............\..\add_sub_1nh.tdf
............................\............\..\add_sub_2nh.tdf
............................\............\..\add_sub_4nh.tdf
............................\............\..\add_sub_5nh.tdf
............................\............\..\add_sub_6nh.tdf
............................\............\..\add_sub_vmh.tdf
............................\............\..\cmp_state.ini
............................\............\..\decode_fib.tdf
............................\............\..\decode_ngb.tdf
............................\............\..\Inter.asm.qmsg
............................\............\..\Inter.cmp.cdb
............................\............\..\Inter.cmp.ddb
............................\............\..\Inter.cmp.hdb
............................\............\..\Inter.cmp.rdb
............................\............\..\Inter.cmp.tdb
............................\............\..\Inter.cmp0.ddb
............................\............\..\Inter.db_info
............................\............\..\Inter.eco.cdb
............................\............\..\Inter.eda.qmsg
............................\............\..\Inter.eds_overflow
............................\............\..\Inter.fit.qmsg
............................\............\..\Inter.fnsim.cdb
............................\............\..\Inter.fnsim.hdb
............................\............\..\Inter.hier_info
............................\............\..\Inter.hif
............................\............\..\Inter.map.cdb
............................\............\..\Inter.map.hdb
............................\............\..\Inter.map.qmsg
............................\............\..\Inter.pre_map.cdb
............................\............\..\Inter.pre_map.hdb
............................\............\..\Inter.psp
............................\............\..\Inter.rtlv.hdb
............................\............\..\Inter.rtlv_sg.cdb
............................\............\..\Inter.rtlv_sg_swap.cdb
............................\............\..\Inter.sgdiff.cdb
............................\............\..\Inter.sgdiff.hdb
............................\............\..\Inter.sim.hdb
............................\............\..\Inter.sim.qmsg
............................\............\..\Inter.sim.rdb
............................\............\..\Inter.sim.vwf
............................\............\..\Inter.sld_design_entry.sci
............................\............\..\Inter.sld_design_entry_dsc.sci
............................\............\..\Inter.syn_hier_info
............................\............\..\Inter.tan.qmsg
............................\............\..\Inter_cmp.qrpt
............................\............\..\Inter_sim.qrpt
............................\............\..\lpm_ram_io0.bsf
............................\............\..\lpm_ram_io0.vhd
............................\............\..\mux_7bc.tdf
............................\............\..\mux_b8c.tdf
............................\............\..\mux_g8c.tdf
............................\............\..\mux_ind.tdf
............................\............\..\mux_vcc.tdf
............................\............\functions.vhd
............................\............\Inter.asm.rpt
............................\............\Inter.bdf
............................\............\inter.bsf
............................\............\Inter.cdf
............................\............\Inter.done
............................\............\Inter.eda.rpt
............................\............\Inter.fit.eqn
............................\............\Inter.fit.r

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