Based on Actel A3P030 FPGA, LCD using JDL12864 serial interface, clock 48MHz

hdl
...\12864_Controller.v
...\CLK_DIV.v
...\C_12864.v
...\Data_Generator.v
...\Decoder.v
...\JDL12864_test.v
...\Reseter.v
...\Shift_24bit.v
...\说明.txt

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