The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation

signal_output
.............\altmult_add1.bsf
.............\altmult_add1.cmp
.............\altmult_add1.vhd

.............\altmult_add1_waveforms.html
.............\altpll1.bsf
.............\altpll1.cmp
.............\altpll1.ppf
.............\altpll1.vhd

.............\altpll1_waveforms.html
.............\clk_counter.bsf
.............\clk_counter.vhd
.............\clk_even_divdier.bsf
.............\clk_even_divdier.vhd
.............\db
.............\..\add_sub_1pe.tdf
.............\..\add_sub_dqg.tdf
.............\..\add_sub_kse.tdf
.............\..\add_sub_lse.tdf
.............\..\add_sub_qbh.tdf
.............\..\add_sub_s7f.tdf
.............\..\decode_aoi.tdf
.............\..\ded_mult_6ke1.tdf
.............\..\ded_mult_74b1.tdf
.............\..\ded_mult_ake1.tdf
.............\..\ded_mult_bke1.tdf
.............\..\ded_mult_me61.tdf
.............\..\ded_mult_n1a1.tdf
.............\..\ded_mult_nie1.tdf
.............\..\ded_mult_ple1.tdf
.............\..\ded_mult_tle1.tdf
.............\..\dffpipe_73c.tdf
.............\..\dffpipe_a3c.tdf
.............\..\dffpipe_d3c.tdf
.............\..\dffpipe_g3c.tdf
.............\..\lpm_constant_h09.tdf
.............\..\mult_add_am33.tdf
.............\..\mult_add_bm33.tdf
.............\..\mult_add_f243.tdf
.............\..\mult_add_nkt2.tdf
.............\..\mult_add_oh23.tdf
.............\..\mult_add_p503.tdf
.............\..\prev_cmp_signal_output.map.qmsg
.............\..\prev_cmp_signal_output.qmsg
.............\..\signal_output.cbx.xml
.............\..\signal_output.cmp.bpm
.............\..\signal_output.cmp.cdb
.............\..\signal_output.cmp.hdb
.............\..\signal_output.cmp.logdb
.............\..\signal_output.cmp.rdb
.............\..\signal_output.dbp
.............\..\signal_output.db_info
.............\..\signal_output.eco.cdb
.............\..\signal_output.fit.qmsg
.............\..\signal_output.hier_info
.............\..\signal_output.hif
.............\..\signal_output.map.bpm
.............\..\signal_output.map.cdb
.............\..\signal_output.map.ecobp
.............\..\signal_output.map.hdb
.............\..\signal_output.map.logdb
.............\..\signal_output.map.qmsg
.............\..\signal_output.map_bb.cdb
.............\..\signal_output.map_bb.hdb
.............\..\signal_output.map_bb.logdb
.............\..\signal_output.merge_hb.atm
.............\..\signal_output.pre_map.cdb
.............\..\signal_output.pre_map.hdb
.............\..\signal_output.psp
.............\..\signal_output.pss
.............\..\signal_output.rtlv.hdb
.............\..\signal_output.rtlv_sg.cdb
.............\..\signal_output.rtlv_sg_swap.cdb
.............\..\signal_output.sgdiff.cdb
.............\..\signal_output.sgdiff.hdb
.............\..\signal_output.sim.cvwf
.............\..\signal_output.sld_design_entry.sci
.............\..\signal_output.sld_design_entry_dsc.sci
.............\..\signal_output.syn_hier_info
.............\..\signal_output.tis_db_list.ddb
.............\..\wed.wsf
.............\fdecode.bsf
.............\fdecode.vhd
.............\ingerate.bsf
.............\ingerate.vhd
.............\lpm_add1.bsf
.............\lpm_add1.cmp
.............\lpm_add1.vhd
.............\LPM_ADD_SUB1.bsf
.............\LPM_ADD_SUB1.cmp
.............\LPM_ADD_SUB1.vhd
.............\lpm_add_sub2.bsf
.............\lpm_add_sub2.cmp
.............\lpm_add_sub2.vhd
.............\lpm_constant1.bsf
.............\lpm_constant1.cmp
.............\lpm_constant1.vhd
.............\lpm_fa.vhd

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