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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 111kb
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  • Author :li***
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Introduction - If you have any usage issues, please Google them yourself
FPGA-based converter, to achieve the conversion between the number of the system is a new beginners are familiar with FPGA-learning good information.
Packet file list
(Preview for download)
switch\db\prev_cmp_test.asm.qmsg
......\..\prev_cmp_test.fit.qmsg
......\..\prev_cmp_test.map.qmsg
......\..\prev_cmp_test.qmsg
......\..\prev_cmp_test.tan.qmsg
......\..\test.asm.qmsg
......\..\test.asm_labs.ddb
......\..\test.cbx.xml
......\..\test.cmp.cdb
......\..\test.cmp.hdb
......\..\test.cmp.logdb
......\..\test.cmp.rdb
......\..\test.cmp.tdb
......\..\test.cmp0.ddb
......\..\test.dbp
......\..\test.db_info
......\..\test.eco.cdb
......\..\test.fit.qmsg
......\..\test.hier_info
......\..\test.hif
......\..\test.map.cdb
......\..\test.map.hdb
......\..\test.map.logdb
......\..\test.map.qmsg
......\..\test.pre_map.cdb
......\..\test.pre_map.hdb
......\..\test.psp
......\..\test.pss
......\..\test.rtlv.hdb
......\..\test.rtlv_sg.cdb
......\..\test.rtlv_sg_swap.cdb
......\..\test.sgdiff.cdb
......\..\test.sgdiff.hdb
......\..\test.signalprobe.cdb
......\..\test.sld_design_entry.sci
......\..\test.sld_design_entry_dsc.sci
......\..\test.syn_hier_info
......\..\test.tan.qmsg
......\..\test.tis_db_list.ddb
......\test.asm.rpt
......\test.cdf
......\test.done
......\test.fit.eqn
......\test.fit.rpt
......\test.fit.smsg
......\test.fit.summary
......\test.flow.rpt
......\test.map.eqn
......\test.map.rpt
......\test.map.summary
......\test.pin
......\test.pof
......\test.qpf
......\test.qsf
......\test.qws
......\test.tan.rpt
......\test.tan.summary
......\test.v
......\test_assignment_defaults.qdf
......\db
switch
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