802.11b simulink simulation source code for PHY layer. It can be used to generate bit-true test vector for RTL level design(FPGA).

80211b-ChEst-06-06-04\BERCounter.m
.....................\ChannelEst.asv
.....................\ChannelEst.m
.....................\demodulator.m
.....................\descrambler.m
.....................\filter_poly.m
.....................\HdrProcess.m
.....................\modulator.m
.....................\parallel2serial.m
.....................\PayloadProcess.m
.....................\PLCP_controller.m
.....................\preamble.m
.....................\ring_buffer.m
.....................\rxPLCP_controller.m
.....................\scrambler.m
.....................\selector.m
.....................\source.m
.....................\test11b.mdl
.....................\TimingEst.asv
.....................\TimingEst.m
.....................\TimingEst_Vincent.m
80211b-ChEst-06-06-04

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