This is a work written in VHDL to read and write dual-port RAM program.

testRAMWR\ADD8B.bsf
.........\ADD8B.vhd
.........\ADD8B.vhd.bak
.........\ADDRESS.bsf
.........\ADDRESS.vhd
.........\ADDRESS.vhd.bak
.........\db\altsyncram_06q1.tdf
.........\..\altsyncram_12e1.tdf
.........\..\altsyncram_47r1.tdf
.........\..\altsyncram_6h92.tdf
.........\..\altsyncram_96c1.tdf
.........\..\altsyncram_el72.tdf
.........\..\altsyncram_nmf1.tdf
.........\..\altsyncram_s5b2.tdf
.........\..\decode_aoi.tdf
.........\..\prev_cmp_testRAMWR.asm.qmsg
.........\..\prev_cmp_testRAMWR.fit.qmsg
.........\..\prev_cmp_testRAMWR.map.qmsg
.........\..\prev_cmp_testRAMWR.qmsg
.........\..\prev_cmp_testRAMWR.sim.qmsg
.........\..\prev_cmp_testRAMWR.tan.qmsg
.........\..\testRAMWR.asm.qmsg
.........\..\testRAMWR.asm_labs.ddb
.........\..\testRAMWR.cbx.xml
.........\..\testRAMWR.cmp.bpm
.........\..\testRAMWR.cmp.cdb
.........\..\testRAMWR.cmp.ecobp
.........\..\testRAMWR.cmp.hdb
.........\..\testRAMWR.cmp.logdb
.........\..\testRAMWR.cmp.rdb
.........\..\testRAMWR.cmp.tdb
.........\..\testRAMWR.cmp0.ddb
.........\..\testRAMWR.cmp2.ddb
.........\..\testRAMWR.db_info
.........\..\testRAMWR.eco.cdb
.........\..\testRAMWR.eds_overflow
.........\..\testRAMWR.fit.qmsg
.........\..\testRAMWR.hier_info
.........\..\testRAMWR.hif
.........\..\testRAMWR.map.bpm
.........\..\testRAMWR.map.cdb
.........\..\testRAMWR.map.ecobp
.........\..\testRAMWR.map.hdb
.........\..\testRAMWR.map.logdb
.........\..\testRAMWR.map.qmsg
.........\..\testRAMWR.map_bb.cdb
.........\..\testRAMWR.map_bb.hdb
.........\..\testRAMWR.map_bb.hdbx
.........\..\testRAMWR.map_bb.logdb
.........\..\testRAMWR.pre_map.cdb
.........\..\testRAMWR.pre_map.hdb
.........\..\testRAMWR.psp
.........\..\testRAMWR.root_partition.cmp.atm
.........\..\testRAMWR.root_partition.cmp.dfp
.........\..\testRAMWR.root_partition.cmp.hdbx
.........\..\testRAMWR.root_partition.cmp.logdb
.........\..\testRAMWR.root_partition.cmp.rcf
.........\..\testRAMWR.root_partition.map.atm
.........\..\testRAMWR.root_partition.map.hdbx
.........\..\testRAMWR.root_partition.map.info
.........\..\testRAMWR.rtlv.hdb
.........\..\testRAMWR.rtlv_sg.cdb
.........\..\testRAMWR.rtlv_sg_swap.cdb
.........\..\testRAMWR.sgdiff.cdb
.........\..\testRAMWR.sgdiff.hdb
.........\..\testRAMWR.signalprobe.cdb
.........\..\testRAMWR.sim.cvwf
.........\..\testRAMWR.sim.hdb
.........\..\testRAMWR.sim.qmsg
.........\..\testRAMWR.sim.rdb
.........\..\testRAMWR.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.atm
.........\..\testRAMWR.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.dfp
.........\..\testRAMWR.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.hdbx
.........\..\testRAMWR.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.logdb
.........\..\testRAMWR.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
.........\..\testRAMWR.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.hdbx
.........\..\testRAMWR.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.logdb
.........\..\testRAMWR.sld_design_entry.sci
.........\..\testRAMWR.sld_design_entry_dsc.sci
.........\..\testRAMWR.syn_hier_info
.........\..\testRAMWR.tan.qmsg
.........\..\testRAMWR.tis_db_list.ddb
.........\..\testRAMWR.tmw_info
.........\..\wed.wsf
.........\Delay.vhd
.........\Delay.vhd.bak
.........\DOUBLRAM.bsf
.........\DOUBLRAM.cmp
.........\DOUBLRAM.inc
.........\DOUBLRAM.qip
.........\DOUBLRAM.vhd
.........\DOUBLRAM_inst.vhd
.........\DOUBLRAM_wave0.jpg
.........\DOUBLRAM_wave1.jpg
.........\DOUBLRAM_waveforms.html
.........\FIFO.bsf
.........\FIFO.cmp
.........\FIFO.inc
.........\FIFO.qip
.........\FIFO.vhd

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