This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.

sdram_vhd_134\brst_cntr.vhd
.............\cslt_cntr.vhd
.............\ihdlutil.vhd
.............\ki_cntr.vhd
.............\mti_pkg.vhd
.............\rcd_cntr.vhd
.............\ref_cntr.vhd
.............\sdrmc_state.vhd
.............\sdrm_tb.vhd
.............\sdrm_t.vhd
.............\sdrm.vhd
.............\sys_int.vhd
.............\vrlgutil.vhd
.............\sdram_vhd_134.ise
.............\readme
.............\sdrm.vcd
.............\sdrm.ucf
.............\micron\ed_comnd.vhd
.............\......\io_utils.vhd
.............\......\mt48lc1m16a1-8a.vhd
.............\......\mti_pkg.vhd
.............\......\stdlogar.vhd
.............\......\test.vhd
.............\......\util1164.vhd
.............\......\vec_gen.vhd
.............\......\readme.txt
.............\......\test.txt

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