16 bit pipeline design by vhdl.

HW5_Source\alu.vhd
..........\brcond.vhd
..........\control.vhd
..........\ext.vhd
..........\forward.vhd
..........\mem_Interface.vhd
..........\myrisc_pipeline_realMem.vhd
..........\myrisc_pipeline_real_top.ucf
..........\myrisc_pipeline_top.vhd
..........\myrisc_pkg.vhd
..........\phase_gen.vhd
..........\reg.vhd
..........\regfile.vhd
..........\shifter.vhd
..........\shl8.vhd
..........\converted\memory_real.v
..........\.........\myrisc_pkg.v
..........\.........\tb_myrisc_pipe_realMem.v
..........\.........\transcript
..........\hint\myrisc_pipeline_realMem.v
..........\....\reg16.v
..........\simulation\data.txt
..........\..........\memory_real.vhd
..........\..........\mycmd_final.txt
..........\..........\tb_myrisc_pipeline_realMem.vhd
...\alu.v
...\brcond.v
...\control.v
...\data.txt
...\forward.v
...\HW5.cr.mti
...\HW5.mpf
...\HW5_report.hwp
...\immext.v
...\memory_real.v
...\mem_Interface.v
...\mycmd_final.txt
...\myrisc_pipeline_realMem.v
...\myrisc_pipeline_top.v
...\myrisc_pkg.txt
...\phase_gen.v
...\reg16.v
...\regfile.v
...\shifter.v
...\shl8.v
...\tb_myrisc_pipe_realMem.v
...\transcript
...\vsim.wlf
...\wave.do
...\.ork\_info
...\....\alu\verilog.asm
...\....\...\_primary.dat
...\....\...\_primary.vhd
...\....\brcond\verilog.asm
...\....\......\_primary.dat
...\....\......\_primary.vhd
...\....\forward\verilog.asm
...\....\.......\_primary.dat
...\....\.......\_primary.vhd
...\....\immext\verilog.asm
...\....\......\_primary.dat
...\....\......\_primary.vhd
...\....\.nstr_decoder\verilog.asm
...\....\.............\_primary.dat
...\....\.............\_primary.vhd
...\....\meminterface_8_16\verilog.asm
...\....\.................\_primary.dat
...\....\.................\_primary.vhd
...\....\...ory\verilog.asm
...\....\......\_primary.dat
...\....\......\_primary.vhd
...\....\.yrisc_pipeline_4ph\verilog.asm
...\....\...................\_primary.dat
...\....\...................\_primary.vhd
...\....\................real_top\verilog.asm
...\....\........................\_primary.dat
...\....\........................\_primary.vhd
...\....\phase_gen\verilog.asm
...\....\.........\_primary.dat
...\....\.........\_primary.vhd
...\....\reg16\verilog.asm
...\....\.....\_primary.dat
...\....\.....\_primary.vhd
...\....\...file\verilog.asm
...\....\.......\_primary.dat
...\....\.......\_primary.vhd
...\....\shifter\verilog.asm
...\....\.......\_primary.dat
...\....\.......\_primary.vhd
...\....\..l8\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\....\.lice\verilog.asm
...\....\.....\_primary.dat
...\....\.....\_primary.vhd
...\....\tb_myrisc_top_real\verilog.asm
...\....\..................\_primary.dat
...\....\..................\_primary.vhd

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