verilog hardware, programming bpsk Modulation

chapter4
........\add_full.v
........\add_half.v
........\count16.v
........\decode3to8.v
........\fifo3.v
........\fre13.v
........\mult1from8.v
........\ram_4_4.v
........\rom_16_4.v
........\ser_to_parr.v
........\trigger_d.v
........\trigger_jk.v
........\trigger_rs.v
chapter5
........\cic_filter_3__28_ho.v
........\cic_insert_3_2_8_ho.v
........\decimate_4.v
........\fir_lp_8.v
........\fir_parr_8.v
........\iir_cascade_2.v
........\iir_filter_8.v
........\insert_4.v
chapter6
........\ask_2.v
........\ask_2_de.v
........\fsk_2.v
........\fsk_2_de.v
........\ppm.v
........\ppm_de.v
........\psk_2.v
........\psk_2_de.v
........\qpsk.v
........\qpsk_de.v
chapter7
........\KESBLOCK.V
........\CSEEBLOCK.v
........\RS_ENCODER.V
........\RSDECODER.v
........\SCBLOCK.V
........\CONTROLLER.v
chapter8
........\8.2节
........\.....\GOLD_SQUE_GEN.v
........\.....\GENSQUE.v
........\8.3节
........\.....\SPR_SPECTRUM_MOD.v
........\8.4节
........\.....\GATE_CONTROL.v.bak
........\.....\SERIAL_SOLVE.v.bak
........\.....\SERIAL_TO_PARALLEL.v.bak
........\.....\GATE_CONTROL.v
........\.....\CATCH_TOP.v.bak
........\.....\CATCH_TOP.v
........\.....\GENSQUE.v.bak
........\.....\GENSQUE.v
........\.....\SERIAL_SOLVE.v
........\.....\SERIAL_TO_PARALLEL.v
........\.....\TESTBENCH.v.bak
........\.....\TESTBENCH.v
chapter9
........\BAUD_GENERATER.v
........\UART_TRANSMITTER.v
........\UART_RECEIVER.v
........\SERIAL_CONTROLLER.v
chapter10
.........\11.2节
.........\......\SCRAMBLER.v
.........\......\SCRAM_TEST.v
.........\......\PARALLER_DESCRAMBLER.v
.........\......\DESCRAMBLER.v
.........\......\PARALLEL_SCRAMBLER.v
.........\......\PARALLEL_SCRAM_TEST.v
.........\11.3节
.........\......\CRC16.v
.........\......\CRC_16_PARALLEL.v
.........\11.4节
.........\......\SDH_STM1.v
.........\11.5节
.........\......\DECODE_8B_10B.v
.........\......\ENCODE_8B_10B.v

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