Using DDS (direct digital frequency synthesis) method, using VHDL written source

!DDS_vhdl\ADDER10B.vhd
.........\ADDER32B.vhd
.........\dataMIF\sin.mif
.........\data_rom.vhd
.........\.b\altsyncram_0ak2.tdf
.........\..\altsyncram_3mi2.tdf
.........\..\altsyncram_pd61.tdf
.........\..\cmpr_gnh.tdf
.........\..\cntr_6he.tdf
.........\..\cntr_daf.tdf
.........\..\cntr_ekf.tdf
.........\..\cntr_fbg.tdf
.........\..\cntr_ngh.tdf
.........\..\DDS_VHDL.db_info
.........\..\DDS_VHDL.sld_design_entry.sci
.........\..\decode_ogi.tdf
.........\..\wed.zsf
.........\DDS_VHDL.asm.rpt
.........\DDS_VHDL.cdf
.........\DDS_VHDL.done
.........\DDS_VHDL.fit.rpt
.........\DDS_VHDL.fit.smsg
.........\DDS_VHDL.fit.summary
.........\DDS_VHDL.flow.rpt
.........\DDS_VHDL.map.rpt
.........\DDS_VHDL.map.summary
.........\DDS_VHDL.pin
.........\DDS_VHDL.pof
.........\DDS_VHDL.qpf
.........\DDS_VHDL.qsf
.........\DDS_VHDL.qws
.........\DDS_VHDL.sim.rpt
.........\DDS_VHDL.sof
.........\dds_vhdl.stp
.........\DDS_VHDL.tan.rpt
.........\DDS_VHDL.tan.summary
.........\DDS_VHDL.vhd
.........\DDS_VHDL.vwf
.........\DDS_VHDL_assignment_defaults.qdf
.........\PLLU.vhd
.........\REG10B.vhd
.........\REG32B.vhd
.........\XY_Dis_Sin.vwf
.........\新建 文本文档.txt
.........\dataMIF
.........\db
!DDS_vhdl

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