VHDL code for bcd7 registry

2\db\prev_cmp_seg7.asm.qmsg
.\..\prev_cmp_seg7.fit.qmsg
.\..\prev_cmp_seg7.map.qmsg
.\..\prev_cmp_seg7.sim.qmsg
.\..\prev_cmp_seg7.tan.qmsg
.\..\seg7.asm.qmsg
.\..\seg7.cbx.xml
.\..\seg7.cmp.cdb
.\..\seg7.cmp.hdb
.\..\seg7.cmp.logdb
.\..\seg7.cmp.rdb
.\..\seg7.cmp.tdb
.\..\seg7.cmp0.ddb
.\..\seg7.dbp
.\..\seg7.db_info
.\..\seg7.eco.cdb
.\..\seg7.fit.qmsg
.\..\seg7.hier_info
.\..\seg7.hif
.\..\seg7.map.cdb
.\..\seg7.map.hdb
.\..\seg7.map.logdb
.\..\seg7.map.qmsg
.\..\seg7.pre_map.cdb
.\..\seg7.pre_map.hdb
.\..\seg7.psp
.\..\seg7.pss
.\..\seg7.rtlv.hdb
.\..\seg7.rtlv_sg.cdb
.\..\seg7.rtlv_sg_swap.cdb
.\..\seg7.sgdiff.cdb
.\..\seg7.sgdiff.hdb
.\..\seg7.sim.cvwf
.\..\seg7.sim.hdb
.\..\seg7.sim.qmsg
.\..\seg7.sim.rdb
.\..\seg7.sld_design_entry.sci
.\..\seg7.sld_design_entry_dsc.sci
.\..\seg7.syn_hier_info
.\..\seg7.tan.qmsg
.\..\wed.wsf
.\prev_cmp_seg7.qmsg
.\seg7.asm.rpt
.\seg7.done
.\seg7.fit.rpt
.\seg7.fit.summary
.\seg7.flow.rpt
.\seg7.map.rpt
.\seg7.map.summary
.\seg7.pin
.\seg7.pof
.\seg7.qpf
.\seg7.qsf
.\seg7.qws
.\seg7.sim.rpt
.\seg7.sof
.\seg7.tan.rpt
.\seg7.tan.summary
.\seg7.vhd
.\seg7.vhd.bak
.\seg7.vwf
.\serv_req_info.txt
.\db
2

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