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74hc4017

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 689kb
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Introduction - If you have any usage issues, please Google them yourself
IC VHDL design
Packet file list
(Preview for download)
74hc4017.pdf
74hc4017
........\4017_module.prj
........\component
........\constraint
........\coreconsole
........\designer
........\........\impl1
........\........\.....\4017model.ide_des
........\........\.....\4017_module.ide_des
........\........\.....\designer.log
........\........\.....\designer_synth_check.log
........\........\.....\model.ide_des
........\........\.....\model4017.adb
........\........\.....\model4017.dtf
........\........\.....\.............\verify.log
........\........\.....\model4017.ide_des
........\........\.....\model4017.pdb
........\........\.....\model4017.pdb.depends
........\........\.....\model4017.tcl
........\........\.....\model4017_ba.sdf
........\........\.....\model4017_ba.sdf_max.csd
........\........\.....\model4017_ba.v
........\........\.....\model4017_fp
........\........\.....\............\$$FlashPro_FPBBALTLPT1.L$$
........\........\.....\............\model4017.log
........\........\.....\............\model4017.pro
........\........\.....\............\projectData
........\........\.....\............\...........\model4017.pdb
........\........\.....\simulation
........\........\.....\..........\postlayout
........\........\.....\..........\..........\model4017
........\........\.....\..........\..........\.........\verilog.psm
........\........\.....\..........\..........\.........\_primary.dat
........\........\.....\..........\..........\.........\_primary.dbs
........\........\.....\..........\..........\.........\_primary.vhd
........\........\.....\..........\..........\stimulus
........\........\.....\..........\..........\........\verilog.psm
........\........\.....\..........\..........\........\_primary.dat
........\........\.....\..........\..........\........\_primary.dbs
........\........\.....\..........\..........\........\_primary.vhd
........\........\.....\..........\..........\tb_clock_minmax
........\........\.....\..........\..........\...............\verilog.psm
........\........\.....\..........\..........\...............\_primary.dat
........\........\.....\..........\..........\...............\_primary.dbs
........\........\.....\..........\..........\...............\_primary.vhd
........\........\.....\..........\..........\testbench
........\........\.....\..........\..........\.........\verilog.psm
........\........\.....\..........\..........\.........\_primary.dat
........\........\.....\..........\..........\.........\_primary.dbs
........\........\.....\..........\..........\.........\_primary.vhd
........\........\.....\..........\..........\_info
........\........\.....\..........\..........\_temp
........\........\.....\..........\..........\_vmake
........\hdl
........\...\4017_module.v
........\phy_synthesis
........\simulation
........\..........\modelsim.ini
........\..........\modelsim.ini.sav
........\..........\modelsim.log
........\..........\postsynth
........\..........\.........\model4017
........\..........\.........\.........\verilog.psm
........\..........\.........\.........\_primary.dat
........\..........\.........\.........\_primary.dbs
........\..........\.........\.........\_primary.vhd
........\..........\.........\stimulus
........\..........\.........\........\verilog.psm
........\..........\.........\........\_primary.dat
........\..........\.........\........\_primary.dbs
........\..........\.........\........\_primary.vhd
........\..........\.........\tb_clock_minmax
........\..........\.........\...............\verilog.psm
........\..........\.........\...............\_primary.dat
........\..........\.........\...............\_primary.dbs
........\..........\.........\...............\_primary.vhd
........\..........\.........\testbench
........\..........\.........\.........\verilog.psm
........\..........\.........\.........\_primary.dat
........\..........\.........\.........\_primary.dbs
........\..........\.........\.........\_primary.vhd
........\..........\.........\_info
........\..........\.........\_temp
........\..........\.........\_vmake
........\..........\presynth
........\..........\........\model
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