Embedded pci bus IP core of the rtl source code, Verilog realization of

pci32tlite_oc_R03
.................\Doc
.................\...\pci32tLite_howto.pdf
.................\...\pci32tLite_oc_um_dm.pdf
.................\historico.hst
.................\lgpl-3.0.txt
.................\Projects
.................\........\maxii_uart
.................\........\..........\Altera
.................\........\..........\......\db
.................\........\..........\......\..\maxii_uart.asm.qmsg
.................\........\..........\......\..\maxii_uart.asm_labs.ddb
.................\........\..........\......\..\maxii_uart.cbx.xml
.................\........\..........\......\..\maxii_uart.cmp.cdb
.................\........\..........\......\..\maxii_uart.cmp.hdb
.................\........\..........\......\..\maxii_uart.cmp.logdb
.................\........\..........\......\..\maxii_uart.cmp.rdb
.................\........\..........\......\..\maxii_uart.cmp.tdb
.................\........\..........\......\..\maxii_uart.cmp0.ddb
.................\........\..........\......\..\maxii_uart.db_info
.................\........\..........\......\..\maxii_uart.eco.cdb
.................\........\..........\......\..\maxii_uart.fit.qmsg
.................\........\..........\......\..\maxii_uart.hier_info
.................\........\..........\......\..\maxii_uart.hif
.................\........\..........\......\..\maxii_uart.map.cdb
.................\........\..........\......\..\maxii_uart.map.hdb
.................\........\..........\......\..\maxii_uart.map.logdb
.................\........\..........\......\..\maxii_uart.map.qmsg
.................\........\..........\......\..\maxii_uart.pre_map.cdb
.................\........\..........\......\..\maxii_uart.pre_map.hdb
.................\........\..........\......\..\maxii_uart.rtlv.hdb
.................\........\..........\......\..\maxii_uart.rtlv_sg.cdb
.................\........\..........\......\..\maxii_uart.rtlv_sg_swap.cdb
.................\........\..........\......\..\maxii_uart.sgdiff.cdb
.................\........\..........\......\..\maxii_uart.sgdiff.hdb
.................\........\..........\......\..\maxii_uart.sld_design_entry.sci
.................\........\..........\......\..\maxii_uart.sld_design_entry_dsc.sci
.................\........\..........\......\..\maxii_uart.smp_dump.txt
.................\........\..........\......\..\maxii_uart.syn_hier_info
.................\........\..........\......\..\maxii_uart.tan.qmsg
.................\........\..........\......\..\maxii_uart.tis_db_list.ddb
.................\........\..........\......\..\maxii_uart.tmw_info
.................\........\..........\......\maxii_uart.asm.rpt
.................\........\..........\......\maxii_uart.done
.................\........\..........\......\maxii_uart.fit.rpt
.................\........\..........\......\maxii_uart.fit.summary
.................\........\..........\......\maxii_uart.flow.rpt
.................\........\..........\......\maxii_uart.map.rpt
.................\........\..........\......\maxii_uart.map.summary
.................\........\..........\......\maxii_uart.pin
.................\........\..........\......\maxii_uart.pof
.................\........\..........\......\maxii_uart.qpf
.................\........\..........\......\maxii_uart.qsf
.................\........\..........\......\maxii_uart.qws
.................\........\..........\......\maxii_uart.tan.rpt
.................\........\..........\......\maxii_uart.tan.summary
.................\........\..........\......\maxii_uart_assignment_defaults.qdf
.................\........\..........\maxii_uart.vhd
.................\Rtl
.................\...\onalib.vhd
.................\...\pci32tlite.vhd
.................\...\pcidec.vhd
.................\...\pcidmux.vhd
.................\...\pcipargen.vhd
.................\...\pciregs.vhd
.................\...\pciwbsequ.vhd

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