This is single cycle 16-bit computer with testbenches written in Verilog. It shows a result based on the instruction memory. I also included documents about the structure of the single cycle computer

alu.v
au1.v
au1_test.v
au16.v
au16_test.v
branch_ctrl.v
datapath.v
datapath_test.v
decoder3to8.v
dut.v
dut_test.v
fsdecoder.v
fu.v
fu_test.v
fulladder-1.v
instr_dec.v
instruction_memory.v
Lab3_March_10_12_MUX.pdf
Lab4_March-17_19_16b_LU-1.pdf
Lab5_March-24_26_Shifter.pdf
Lab6_April-7_9_AU.pdf
Lab7_April-14_16_FU.pdf
Lab8_April-21_23_RF_DP.pdf
Lab9_April-28_30_ID_Mem-3.pdf
Lab10_May_5_7_PC.pdf
Lab11_May_12_14_SingleCycleComputer.pdf
lu1.v
lu1_test.v
lu16.v
lu16_test.v
mem.v
mux2.v
mux2_16b.v
mux2_test.v
mux3_16b.v
mux4.v
mux4_test.v
mux8.v
mux8_test.v
mux81_behav.v
offset.v
pc.v
pc_test.v
reg_load.v
reg16.v
regsterfile.v
scc16b.v
scc16b_test.v
shf16.v
shf16_test.v
shift1.v
ygen.v
zerofill.v

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