8 bit RSIC CPU RTL code(Verilog)

8位RISC CPU 内核源码(VERILOG版)\使用说明请参看右侧注释====〉〉.txt
...............................\alu.v
...............................\basic.asm
...............................\BASIC.HEX
...............................\basic.rom
...............................\COPYING
...............................\cpu.v
...............................\dds.asm
...............................\DDS.HEX
...............................\dds.rom
...............................\dram.v
...............................\exp.v
...............................\hex2v.c
...............................\idec.v
...............................\pram.v
...............................\regs.v
...............................\risc8.gif
...............................\risc8doc.html
...............................\runit
...............................\sindata.c
...............................\sindata.hex
...............................\test.v
...............................\transcript
8位RISC CPU 内核源码(VERILOG版)

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