Introduction - If you have any usage issues, please Google them yourself
Clock Controller
There are often situations where one wishes to pass a predetermined number of clock pulses and then stop. The purpose of this problem is to design a controller in VHDL to gate a preset number of pulses form a free-running clock “CLK”. Your design should pass a predetermined number of pulses to an output “POUT” and then stop, without producing any shortened pulses or glitches. Your circuit should have an 8 position DIP Switch for setting a number “N” and a free running clock input that has a frequency is of 2.55 Mhz . The “START” signal is an asynchronous input signal which will initiate the generator such that when the start button is pushed exactly N clock pulses would be passed to the output “POUT”.