When the DLL_FREQUENCY_MODE attribute is set to High, the frequency of the clock signal at the CLKIN input must be in the High (DLL_CLKIN_MIN_HF to DLL_CLKIN_MAX_HF) frequency range (MHz). See The Programmable Logic Data Book for the current DLL_CLKIN_MIN_HF to DLL_CLKIN_MAX_HF frequency range values. In High frequency mode, only the CLK0, CLK180, and CLKDV outputs are available.

wtut_vhd\clk_div_262k.vhd
........\create_wtut_vhd.tcl
........\debounce.vhd
........\led_control.vhd
........\statmach.vhd
........\stopwatch.vhd
........\stopwatch.xcf
........\time_cnt.vhd
wtut_vhd
........\stopwatch_tb.vhd
........\wtut_vhd_completed
........\..................\create_wtut_vhd.tcl
........\..................\dcm1.v
........\..................\dcm1.xaw
........\..................\dcm1_arwz.ucf
........\..................\debounce.vhd
........\..................\hex2led.vhd
........\..................\led_control.vhd
........\..................\statmach.vhd
........\..................\stopwatch.vhd
........\..................\stopwatch_tb.vhd
........\..................\ten_cnt.edn
........\..................\ten_cnt.ngo
........\..................\ten_cnt.sym
........\..................\ten_cnt.v
........\..................\ten_cnt.veo
........\..................\ten_cnt.vhd
........\..................\ten_cnt.vho
........\..................\ten_cnt.xco
........\..................\ten_cnt_c_counter_binary_v9_0_xst_1.ngc
........\..................\ten_cnt_flist.txt
........\..................\time_cnt.vhd
........\..................\clk_div_262k.vhd

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