Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file

bram_delay\.lso
..........\blk_mem_gen_ds512.pdf
..........\blk_mem_gen_release_notes.txt
..........\bram_16.asy
..........\bram_16.ngc
..........\bram_16.sym
..........\bram_16.v
..........\bram_16.veo
..........\bram_16.vhd
..........\bram_16.vho
..........\bram_16.xco
..........\bram_16_blk_mem_gen_v2_4_xst_1.lso
..........\bram_16_blk_mem_gen_v2_4_xst_1_vhdl.prj
..........\bram_16_flist.txt
..........\bram_16_readme.txt
..........\bram_16_xmdf.tcl
..........\bram_delay.doc
..........\bram_delay.ise
..........\bram_delay.ise_ISE_Backup
..........\bram_delay.prj
..........\bram_delay.restore
..........\bram_delay.stx
..........\bram_delay.v
..........\bram_delay.xst
..........\bram_delay_summary.html
..........\isim\temp\hdllib.ref
..........\....\....\hdpdeps.ref
..........\....\....\vlg06\tb__bram__delay__v.bin
..........\....\....\....8\bram__16.bin
..........\....\....\...2D\glbl.bin
..........\....\....\...48\bram__delay.bin
..........\....\work\bram__16\bram__16.h
..........\....\....\........\mingw\bram__16.obj
..........\....\....\......delay\bram__delay.h
..........\....\....\...........\mingw\bram__delay.obj
..........\....\....\glbl\glbl.h
..........\....\....\....\mingw\glbl.obj
..........\....\....\hdllib.ref
..........\....\....\hdpdeps.ref
..........\....\....\tb__bram__delay__v\mingw\tb__bram__delay__v.obj
..........\....\....\..................\tb__bram__delay__v.h
..........\....\....\..................\xsimtb__bram__delay__v.cpp
..........\....\....\.st__bram__delay__v\mingw\tst__bram__delay__v.obj
..........\....\....\...................\tst__bram__delay__v.h
..........\....\....\...................\xsimtst__bram__delay__v.cpp
..........\....\....\vlg06\tb__bram__delay__v.bin
..........\....\....\....8\bram__16.bin
..........\....\....\...2D\glbl.bin
..........\....\....\...48\bram__delay.bin
..........\....\....\...7B\tst__bram__delay__v.bin
..........\....\xilinxcorelib_ver.auxlib\hdllib.ref
..........\....\........................\_b_l_k___m_e_m___g_e_n___v2__4\mingw\_b_l_k___m_e_m___g_e_n___v2__4.obj
..........\....\........................\..............................\_b_l_k___m_e_m___g_e_n___v2__4.h
..........\....\........................\..............................__output__stage\mingw\_b_l_k___m_e_m___g_e_n___v2__4__output__stage.obj
..........\....\........................\.............................................\_b_l_k___m_e_m___g_e_n___v2__4__output__stage.h
..........\isim.cmd
..........\isim.hdlsourcefiles
..........\isim.log
..........\.....tmp_save\_1
..........\isimwavedata.xwv
..........\simulate_dofile.log
..........\simulate_dofile.log_back
..........\tb_bram_delay.v
..........\tb_bram_delay_v_beh.prj
..........\tb_bram_delay_v_isim_beh.exe
..........\tb_bram_delay_v_isim_beh.wfs
..........\tb_bram_delay_v_stx.prj
..........\.emplates\coregen.xml
..........\tst_bram_delay.v
..........\tst_bram_delay_v_isim_beh.wfs
..........\xilinxsim.ini
..........\.st\work\hdllib.ref
..........\...\....\vlg48\bram__delay.bin
..........\_xmsgs\fuse.xmsgs
..........\......\xst.xmsgs
..........\__ISE_repository_bram_delay.ise_.lock
..........\isim\work\bram__16\mingw
..........\....\....\......delay\mingw
..........\....\....\glbl\mingw
..........\....\....\tb__bram__delay__v\mingw
..........\....\....\.st__bram__delay__v\mingw
..........\....\xilinxcorelib_ver.auxlib\_b_l_k___m_e_m___g_e_n___v2__4\mingw
..........\....\........................\..............................__output__stage\mingw
..........\....\temp\vlg06
..........\....\....\vlg08
..........\....\....\vlg2D
..........\....\....\vlg48
..........\....\work\bram__16
..........\....\....\bram__delay
..........\....\....\glbl
..........\....\....\tb__bram__delay__v
..........\....\....\tst__bram__delay__v
..........\....\....\vlg06
..........\....\....\vlg08
..........\....\....\vlg2D
..........\....\....\vlg48
..........\....\....\vlg7B
..........\....\xilinxcorelib_ver.auxlib\_b_l_k___m_e_m___g_e_n___v2__4
..........\....\........................\_b_l_k___m_e_m___g_e_n___v2__4__output__stage
..........\xst\work\vlg48

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