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floating_multi

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.7mb
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Floating point multiplier
Packet file list
(Preview for download)
floating_multi\CH7_Slides.pdf
..............\fpmul.zip
..............\fpmul.doc
..............\SynTestbed.v
..............\constants.v
..............\exponent.v
..............\flag.v
..............\fpmul.v
..............\multiply.v
..............\normalize.v
..............\prenorm.v
..............\prenormshift.v
..............\preprocess.v
..............\round.v
..............\shift.v
..............\special.v
..............\assemble.v
..............\fpmul.dcs
..............\work\_info
..............\....\special\_primary.vhd
..............\....\.......\verilog.asm
..............\....\.......\_primary.dat
..............\....\.hift\_primary.vhd
..............\....\.....\verilog.asm
..............\....\.....\_primary.dat
..............\....\round\_primary.vhd
..............\....\.....\verilog.asm
..............\....\.....\_primary.dat
..............\....\preprocess\_primary.vhd
..............\....\..........\verilog.asm
..............\....\..........\_primary.dat
..............\....\...norm\_primary.vhd
..............\....\.......\verilog.asm
..............\....\.......\_primary.dat
..............\....\normalize\_primary.vhd
..............\....\.........\verilog.asm
..............\....\.........\_primary.dat
..............\....\multiply\_primary.vhd
..............\....\........\verilog.asm
..............\....\........\_primary.dat
..............\....\fpmul\_primary.vhd
..............\....\.....\verilog.asm
..............\....\.....\_primary.dat
..............\....\.lag\_primary.vhd
..............\....\....\verilog.asm
..............\....\....\_primary.dat
..............\....\exponent\_primary.vhd
..............\....\........\verilog.asm
..............\....\........\_primary.dat
..............\....\assemble\_primary.vhd
..............\....\........\verilog.asm
..............\....\........\_primary.dat
..............\....\flop\_primary.vhd
..............\....\....\verilog.asm
..............\....\....\_primary.dat
..............\....\@syn@testbed\_primary.vhd
..............\....\............\verilog.asm
..............\....\............\_primary.dat
..............\....\.t@e@s@t\_primary.vhd
..............\....\........\verilog.asm
..............\....\........\_primary.dat
..............\....\tb_fpadd\_primary.vhd
..............\....\........\verilog.asm
..............\....\........\_primary.dat
..............\....\.....mult\_primary.vhd
..............\....\.........\verilog.asm
..............\....\.........\_primary.dat
..............\....\_opt\work__info
..............\....\....\_deps
..............\....\....\work_preprocess_fast.asm
..............\....\....\work_preprocess_fast.dt2
..............\....\....\work_special_fast.asm
..............\....\....\work_special_fast.dt2
..............\....\....\work_prenorm_fast.asm
..............\....\....\work_prenorm_fast.dt2
..............\....\....\work_multiply_fast.asm
..............\....\....\work_multiply_fast.dt2
..............\....\....\work_exponent_fast.asm
..............\....\....\work_exponent_fast.dt2
..............\....\....\work_normalize_fast.asm
..............\....\....\work_normalize_fast.dt2
..............\....\....\work_shift_fast.asm
..............\....\....\work_shift_fast.dt2
..............\....\....\work_round_fast.asm
..............\....\....\work_round_fast.dt2
..............\....\....\work_flag_fast.asm
..............\....\....\work_flag_fast.dt2
..............\....\....\work_assemble_fast.asm
..............\....\....\work_assemble_fast.dt2
..............\....\....\work_fpmul_fast.asm
..............\....\....\work_fpmul_fast.dt2
..............\....\....\work_tb_fpmult_fast.asm
..............\....\....\work_tb_fpmult_fast.dt2
..............\Ieee754Mult.pdf
..............\fpmul_doc.doc
..............\transcript
..............\tb_fpmult.v.bak
..............\tb_fpmult.v
..............\data1.dat
..............\result.dat
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