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  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 558kb
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  • Author :al***
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Introduction - If you have any usage issues, please Google them yourself
Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube showed the delicate, seconds, minutes. Has started, pause, reset. Learning VerilogHDL classic example of adding a display.
Packet file list
(Preview for download)
paobiao\.sopc_builder\filters.xml
.......\channelselect.bsf
.......\channelselect.v
.......\channelselect.v.bak
.......\clkdivide.bsf
.......\clkdivide.v
.......\clkdivide.v.bak
.......\db\logic_util_heursitic.dat
.......\..\mux_joc.tdf
.......\..\paobiao.asm.qmsg
.......\..\paobiao.asm.rdb
.......\..\paobiao.asm_labs.ddb
.......\..\paobiao.cbx.xml
.......\..\paobiao.cmp.bpm
.......\..\paobiao.cmp.cdb
.......\..\paobiao.cmp.ecobp
.......\..\paobiao.cmp.hdb
.......\..\paobiao.cmp.kpt
.......\..\paobiao.cmp.logdb
.......\..\paobiao.cmp.rdb
.......\..\paobiao.cmp.tdb
.......\..\paobiao.cmp0.ddb
.......\..\paobiao.cmp2.ddb
.......\..\paobiao.cmp_merge.kpt
.......\..\paobiao.db_info
.......\..\paobiao.eco.cdb
.......\..\paobiao.eds_overflow
.......\..\paobiao.fit.qmsg
.......\..\paobiao.fnsim.hdb
.......\..\paobiao.fnsim.qmsg
.......\..\paobiao.hier_info
.......\..\paobiao.hif
.......\..\paobiao.lpc.html
.......\..\paobiao.lpc.rdb
.......\..\paobiao.lpc.txt
.......\..\paobiao.map.bpm
.......\..\paobiao.map.cdb
.......\..\paobiao.map.ecobp
.......\..\paobiao.map.hdb
.......\..\paobiao.map.kpt
.......\..\paobiao.map.logdb
.......\..\paobiao.map.qmsg
.......\..\paobiao.map_bb.cdb
.......\..\paobiao.map_bb.hdb
.......\..\paobiao.map_bb.logdb
.......\..\paobiao.pre_map.cdb
.......\..\paobiao.pre_map.hdb
.......\..\paobiao.rtlv.hdb
.......\..\paobiao.rtlv_sg.cdb
.......\..\paobiao.rtlv_sg_swap.cdb
.......\..\paobiao.sgdiff.cdb
.......\..\paobiao.sgdiff.hdb
.......\..\paobiao.sim.cvwf
.......\..\paobiao.sim.hdb
.......\..\paobiao.sim.qmsg
.......\..\paobiao.sim.rdb
.......\..\paobiao.simfam
.......\..\paobiao.sld_design_entry.sci
.......\..\paobiao.sld_design_entry_dsc.sci
.......\..\paobiao.smart_action.txt
.......\..\paobiao.syn_hier_info
.......\..\paobiao.tan.qmsg
.......\..\paobiao.tis_db_list.ddb
.......\..\paobiao.tmw_info
.......\..\prev_cmp_paobiao.asm.qmsg
.......\..\prev_cmp_paobiao.fit.qmsg
.......\..\prev_cmp_paobiao.map.qmsg
.......\..\prev_cmp_paobiao.qmsg
.......\..\prev_cmp_paobiao.sim.qmsg
.......\..\prev_cmp_paobiao.tan.qmsg
.......\..\wed.wsf
.......\..\_7seg_decoder.v
.......\DE2_Board.pin
.......\decoder_7seg.bsf
.......\decoder_7seg.v
.......\decoder_7seg.v.bak
.......\incremental_db\compiled_partitions\paobiao.root_partition.cmp.cdb
.......\..............\...................\paobiao.root_partition.cmp.dfp
.......\..............\...................\paobiao.root_partition.cmp.hdb
.......\..............\...................\paobiao.root_partition.cmp.kpt
.......\..............\...................\paobiao.root_partition.cmp.logdb
.......\..............\...................\paobiao.root_partition.cmp.rcfdb
.......\..............\...................\paobiao.root_partition.cmp.re.rcfdb
.......\..............\...................\paobiao.root_partition.map.cdb
.......\..............\...................\paobiao.root_partition.map.dpi
.......\..............\...................\paobiao.root_partition.map.hdb
.......\..............\...................\paobiao.root_partition.map.kpt
.......\..............\README
.......\paobiao.asm.rpt
.......\paobiao.bdf
.......\paobiao.bsf
.......\paobiao.cdf
.......\paobiao.done
.......\paobiao.dpf
.......\paobiao.fit.rpt
.......\paobiao.fit.smsg
.......\paobiao.fit.summary
.......\paobiao.flow.rpt
.......\paobiao.map.rpt
.......\paobiao.map.smsg
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