After QuartusII their written procedures for verification of the Verilog HDL, can achieve common features

十个位分离.v
秒表计时器\clear.v
..........\control.v
..........\displaydigital.v
..........\frequency1.v
..........\secondclk.v
按键去抖动.v
分频器1.v
分频器2.v
红绿灯控制器.v
七段数码显示器.v
秒表计时器

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