this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given

Processor_alu
.............\alu_top.v
.............\alu_control_tbw.tfw
.............\IF_alu.v
.............\DC_alu.v
.............\EX_alu.v
.............\alu_control.v

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．