Verilog EDA dianti

新建文件夹 (2)\bcudhcdih\123.qpf
..............\.........\123.qsf
..............\.........\123.qws
..............\.........\123.vwf
..............\.........\Block1.bdf
..............\.........\cmp_state.ini
..............\.........\contrl.asm.rpt
..............\.........\contrl.bsf
..............\.........\contrl.cdf
..............\.........\contrl.done
..............\.........\contrl.fit.eqn
..............\.........\contrl.fit.rpt
..............\.........\contrl.fit.summary
..............\.........\contrl.flow.rpt
..............\.........\contrl.map.eqn
..............\.........\contrl.map.rpt
..............\.........\contrl.map.summary
..............\.........\contrl.pin
..............\.........\contrl.pof
..............\.........\contrl.qpf
..............\.........\contrl.qsf
..............\.........\contrl.qws
..............\.........\contrl.sim.rpt
..............\.........\contrl.sof
..............\.........\contrl.tan.rpt
..............\.........\contrl.tan.summary
..............\.........\contrl.vhd
..............\.........\contrl.vwf
..............\.........\db\123.cbx.xml
..............\.........\..\123.db_info
..............\.........\..\123.eco.cdb
..............\.........\..\123.map.qmsg
..............\.........\..\123.sim.qmsg
..............\.........\..\123.sld_design_entry.sci
..............\.........\..\123.sld_design_entry_dsc.sci
..............\.........\..\add_sub_3rh.tdf
..............\.........\..\add_sub_4rh.tdf
..............\.........\..\contrl.asm.qmsg
..............\.........\..\contrl.cbx.xml
..............\.........\..\contrl.cmp.rdb
..............\.........\..\contrl.db_info
..............\.........\..\contrl.eco.cdb
..............\.........\..\contrl.eds_overflow
..............\.........\..\contrl.fit.qmsg
..............\.........\..\contrl.fnsim.hdb
..............\.........\..\contrl.hier_info
..............\.........\..\contrl.hif
..............\.........\..\contrl.map.hdb
..............\.........\..\contrl.map.qmsg
..............\.........\..\contrl.pre_map.hdb
..............\.........\..\contrl.psp
..............\.........\..\contrl.rtlv.hdb
..............\.........\..\contrl.rtlv_sg.cdb
..............\.........\..\contrl.rtlv_sg_swap.cdb
..............\.........\..\contrl.sgdiff.cdb
..............\.........\..\contrl.sgdiff.hdb
..............\.........\..\contrl.sim.hdb
..............\.........\..\contrl.sim.qmsg
..............\.........\..\contrl.sim.rdb
..............\.........\..\contrl.sim.vwf
..............\.........\..\contrl.sld_design_entry.sci
..............\.........\..\contrl.sld_design_entry_dsc.sci
..............\.........\..\contrl.smp_dump.txt
..............\.........\..\contrl.syn_hier_info
..............\.........\..\contrl.tan.qmsg
..............\.........\..\contrl_cmp.qrpt
..............\.........\..\contrl_sim.qrpt
..............\.........\library iee1.doc
..............\电梯运行控制器实验报告.doc
..............\bcudhcdih\db
..............\bcudhcdih
新建文件夹 (2)

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