A UART module writen in VHDL.

UARTE\cmp_state.ini
.....\db\UARTE.asm.qmsg
.....\..\UARTE.asm_labs.ddb
.....\..\UARTE.cbx.xml
.....\..\UARTE.cmp.cdb
.....\..\UARTE.cmp.hdb
.....\..\UARTE.cmp.kpt
.....\..\UARTE.cmp.logdb
.....\..\UARTE.cmp.rdb
.....\..\UARTE.cmp.tdb
.....\..\UARTE.cmp0.ddb
.....\..\UARTE.cmp2.ddb
.....\..\UARTE.db_info
.....\..\UARTE.eco.cdb
.....\..\UARTE.fit.qmsg
.....\..\UARTE.hier_info
.....\..\UARTE.hif
.....\..\UARTE.lpc.html
.....\..\UARTE.lpc.rdb
.....\..\UARTE.lpc.txt
.....\..\UARTE.map.cdb
.....\..\UARTE.map.hdb
.....\..\UARTE.map.logdb
.....\..\UARTE.map.qmsg
.....\..\UARTE.pre_map.cdb
.....\..\UARTE.pre_map.hdb
.....\..\UARTE.rtlv.hdb
.....\..\UARTE.rtlv_sg.cdb
.....\..\UARTE.rtlv_sg_swap.cdb
.....\..\UARTE.sgdiff.cdb
.....\..\UARTE.sgdiff.hdb
.....\..\UARTE.sim.vwf
.....\..\UARTE.sld_design_entry.sci
.....\..\UARTE.sld_design_entry_dsc.sci
.....\..\UARTE.syn_hier_info
.....\..\UARTE.tan.qmsg
.....\..\UARTE.tis_db_list.ddb
.....\..\UARTE.tmw_info
.....\..\UARTE_cmp.qrpt
.....\..\UARTE_global_asgn_op.abo
.....\..\UARTE_sim.qrpt
.....\incremental_db\compiled_partitions\UARTE.root_partition.map.kpt
.....\..............\README
.....\UARTE.asm.rpt
.....\UARTE.cdf
.....\UARTE.done
.....\UARTE.fit.eqn
.....\UARTE.fit.rpt
.....\UARTE.fit.smsg
.....\UARTE.fit.summary
.....\UARTE.fld
.....\UARTE.flow.rpt
.....\UARTE.map.eqn
.....\UARTE.map.rpt
.....\UARTE.map.summary
.....\UARTE.pin
.....\UARTE.pof
.....\UARTE.qpf
.....\UARTE.qsf
.....\UARTE.qws
.....\UARTE.sim.rpt
.....\UARTE.sof
.....\UARTE.tan.rpt
.....\UARTE.tan.summary
.....\UARTE.vhd
.....\UARTE.vwf
.....\UARTE_assignment_defaults.qdf
.....\incremental_db\compiled_partitions
.....\db
.....\incremental_db
UARTE

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