Cyclone EP1C6240C8 FPGA-based interface program of the ADS2807, ADS2807 is mainly used to control the use of FPGA collection. ADS2807 with FPGA to simulate the timing to achieve control functions. To provide sampling frequency control, AD-channel conversion, sampled-data caching and other functions.

FPGA_AD\Block1.bdf
.......\db\add_sub_3ph.tdf
.......\..\add_sub_jsh.tdf
.......\..\FPGA_AD.cbx.xml
.......\..\FPGA_AD.cmp.rdb
.......\..\FPGA_AD.cmp_merge.kpt
.......\..\FPGA_AD.db_info
.......\..\FPGA_AD.eco.cdb
.......\..\FPGA_AD.eds_overflow
.......\..\FPGA_AD.fnsim.cdb
.......\..\FPGA_AD.fnsim.hdb
.......\..\FPGA_AD.fnsim.qmsg
.......\..\FPGA_AD.hier_info
.......\..\FPGA_AD.hif
.......\..\FPGA_AD.lpc.html
.......\..\FPGA_AD.lpc.rdb
.......\..\FPGA_AD.lpc.txt
.......\..\FPGA_AD.map.bpm
.......\..\FPGA_AD.map.cdb
.......\..\FPGA_AD.map.ecobp
.......\..\FPGA_AD.map.hdb
.......\..\FPGA_AD.map.kpt
.......\..\FPGA_AD.map.logdb
.......\..\FPGA_AD.map.qmsg
.......\..\FPGA_AD.map_bb.cdb
.......\..\FPGA_AD.map_bb.hdb
.......\..\FPGA_AD.map_bb.logdb
.......\..\FPGA_AD.pre_map.cdb
.......\..\FPGA_AD.pre_map.hdb
.......\..\FPGA_AD.rpp.qmsg
.......\..\FPGA_AD.rtlv.hdb
.......\..\FPGA_AD.rtlv_sg.cdb
.......\..\FPGA_AD.rtlv_sg_swap.cdb
.......\..\FPGA_AD.sgate.rvd
.......\..\FPGA_AD.sgate_sm.rvd
.......\..\FPGA_AD.sgdiff.cdb
.......\..\FPGA_AD.sgdiff.hdb
.......\..\FPGA_AD.sim.cvwf
.......\..\FPGA_AD.sim.hdb
.......\..\FPGA_AD.sim.qmsg
.......\..\FPGA_AD.sim.rdb
.......\..\FPGA_AD.simfam
.......\..\FPGA_AD.sld_design_entry.sci
.......\..\FPGA_AD.sld_design_entry_dsc.sci
.......\..\FPGA_AD.smp_dump.txt
.......\..\FPGA_AD.syn_hier_info
.......\..\FPGA_AD.tis_db_list.ddb
.......\..\FPGA_AD.tmw_info
.......\..\prev_cmp_FPGA_AD.map.qmsg
.......\..\prev_cmp_FPGA_AD.qmsg
.......\..\prev_cmp_FPGA_AD.sim.qmsg
.......\..\wed.wsf
.......\FPGA_AD.bsf
.......\FPGA_AD.done
.......\FPGA_AD.flow.rpt
.......\FPGA_AD.map.rpt
.......\FPGA_AD.map.smsg
.......\FPGA_AD.map.summary
.......\FPGA_AD.qpf
.......\FPGA_AD.qsf
.......\FPGA_AD.qws
.......\FPGA_AD.sim.rpt
.......\FPGA_AD.v
.......\FPGA_AD.v.bak
.......\FPGA_AD.vwf
.......\incremental_db\compiled_partitions\FPGA_AD.root_partition.map.atm
.......\..............\...................\FPGA_AD.root_partition.map.dpi
.......\..............\...................\FPGA_AD.root_partition.map.hdbx
.......\..............\...................\FPGA_AD.root_partition.map.kpt
.......\..............\README
.......\..............\compiled_partitions
.......\db
.......\incremental_db
FPGA_AD

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