VHDL language design with 24-hour counters, and digital tube display

24小时计数器\db\add_sub_0ih.tdf
............\..\shizhong4.db_info
............\..\shizhong4.eco.cdb
............\..\shizhong4.sld_design_entry.sci
............\shizhong4.asm.rpt
............\shizhong4.cdf
............\shizhong4.done
............\shizhong4.fit.eqn
............\shizhong4.fit.rpt
............\shizhong4.fit.summary
............\shizhong4.flow.rpt
............\shizhong4.map.eqn
............\shizhong4.map.rpt
............\shizhong4.map.summary
............\shizhong4.pin
............\shizhong4.pof
............\shizhong4.qpf
............\shizhong4.qsf
............\shizhong4.qws
............\shizhong4.sof
............\shizhong4.tan.rpt
............\shizhong4.tan.summary
............\shizhong4.vhd
............\shizhong4.vhd.bak
............\shizhong4_assignment_defaults.qdf
............\db
24小时计数器

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